fa98ac6893f8a2919c3a974a916889cc8757427b
[riscv-isa-sim.git] / riscv / insns / rem.h
1 sreg_t lhs = sext_xprlen(RS1);
2 sreg_t rhs = sext_xprlen(RS2);
3 if(rhs == 0)
4 WRITE_RD(lhs);
5 else if(lhs == INT64_MIN && rhs == -1)
6 WRITE_RD(0);
7 else
8 WRITE_RD(sext_xprlen(lhs % rhs));