c29194732f00d93415df95368052bbef2e3ec4cf
[riscv-isa-sim.git] / riscv / insns / remu.h
1 reg_t lhs = zext_xlen(RS1);
2 reg_t rhs = zext_xlen(RS2);
3 if(rhs == 0)
4 WRITE_RD(sext_xlen(RS1));
5 else
6 WRITE_RD(sext_xlen(lhs % rhs));