e74774cc23d01baf018971b9b9e75a44d6001025
[riscv-isa-sim.git] / riscv / insns / remu.h
1 require_extension('M');
2 reg_t lhs = zext_xlen(RS1);
3 reg_t rhs = zext_xlen(RS2);
4 if(rhs == 0)
5 WRITE_RD(sext_xlen(RS1));
6 else
7 WRITE_RD(sext_xlen(lhs % rhs));