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820a396e011e016028f6c96525fe413efa2fb84d
[riscv-isa-sim.git]
/
riscv
/
insns
/
remuw.h
1
if
(
uint32_t
(
RS2
) ==
0
)
2
RD
=
0
;
3
else
4
RD
=
sext32
(
uint32_t
(
RS1
) %
uint32_t
(
RS2
));