bec7059c1ebea7196027a02b9da31f50e5edc399
[riscv-isa-sim.git] / riscv / insns / remuw.h
1 require_xpr64;
2 reg_t lhs = zext32(RS1);
3 reg_t rhs = zext32(RS2);
4 if(rhs == 0)
5 WRITE_RD(sext32(lhs));
6 else
7 WRITE_RD(sext32(lhs % rhs));