56221ccd4e742dbe142858d0e7739c182c95818a
[riscv-isa-sim.git] / riscv / insns / remw.h
1 require_extension('M');
2 require_rv64;
3 sreg_t lhs = sext32(RS1);
4 sreg_t rhs = sext32(RS2);
5 if(rhs == 0)
6 WRITE_RD(lhs);
7 else
8 WRITE_RD(sext32(lhs % rhs));