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3b4824445c77a6a148fde9a231ba5d52852e8b3c
[riscv-isa-sim.git]
/
riscv
/
insns
/
sc_d.h
1
require_xpr64
;
2
if
(
RS1
==
p
->
get_state
()->
load_reservation
)
3
{
4
MMU
.
store_uint64
(
RS1
,
RS2
);
5
WRITE_RD
(
0
);
6
}
7
else
8
WRITE_RD
(
1
);