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29640bfb2a6865eff0aa98d50425f2453f7dc563
[riscv-isa-sim.git]
/
riscv
/
insns
/
sraw.h
1
require_xpr64
;
2
WRITE_RD
(
sext32
(
int32_t
(
RS1
) >> (
RS2
&
0x1F
)));