442b00b3545090e89af3fcd1e870a49bf3252ab0
[riscv-isa-sim.git] / riscv / insns / sret.h
1 require_supervisor;
2 p->set_pcr(CSR_STATUS, ((p->get_state()->sr & ~(SR_S | SR_EI)) |
3 ((p->get_state()->sr & SR_PS) ? SR_S : 0)) |
4 ((p->get_state()->sr & SR_PEI) ? SR_EI : 0));
5 set_pc(p->get_state()->epc);