dc2fee0fb0771385d671c2b9435d2d76a26897ae
[riscv-isa-sim.git] / riscv / insns / sret.h
1 require_privilege(PRV_S);
2 set_pc_and_serialize(p->get_state()->sepc);
3 reg_t s = STATE.mstatus;
4 reg_t prev_prv = get_field(s, MSTATUS_SPP);
5 s = set_field(s, MSTATUS_UIE << prev_prv, get_field(s, MSTATUS_SPIE));
6 s = set_field(s, MSTATUS_SPIE, 0);
7 s = set_field(s, MSTATUS_SPP, PRV_U);
8 p->set_privilege(prev_prv);
9 p->set_csr(CSR_MSTATUS, s);
10
11 /* We're not in Debug Mode anymore. */
12 STATE.dcsr.cause = 0;