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c3a43cf4b627510267e9303fbef1c46821b3180b
[riscv-isa-sim.git]
/
riscv
/
insns
/
vf.h
1
require_vector
;
2
for
(
int
i
=
0
;
i
<
VL
;
i
++)
3
{
4
uts
[
i
]->
pc
=
RS1
+
SIMM
;
5
uts
[
i
]->
utmode
=
true
;
6
while
(
uts
[
i
]->
utmode
)
7
uts
[
i
]->
step
(
n
,
noisy
);
8
}