b18a6fa9501b131562644b97d0c30ef6d9a58598
1 // See LICENSE for license details.
21 static std::string
readline(int fd
)
24 bool noncanonical
= tcgetattr(fd
, &tios
) == 0 && (tios
.c_lflag
& ICANON
) == 0;
27 for (char ch
; read(fd
, &ch
, 1) == 1; )
35 if (noncanonical
&& write(fd
, "\b \b", 3) != 3)
38 else if (noncanonical
&& write(fd
, &ch
, 1) != 1)
49 void sim_t::interactive()
51 typedef void (sim_t::*interactive_func
)(const std::string
&, const std::vector
<std::string
>&);
52 std::map
<std::string
,interactive_func
> funcs
;
54 funcs
["r"] = &sim_t::interactive_run_noisy
;
55 funcs
["rs"] = &sim_t::interactive_run_silent
;
56 funcs
["reg"] = &sim_t::interactive_reg
;
57 funcs
["fregs"] = &sim_t::interactive_fregs
;
58 funcs
["fregd"] = &sim_t::interactive_fregd
;
59 funcs
["mem"] = &sim_t::interactive_mem
;
60 funcs
["str"] = &sim_t::interactive_str
;
61 funcs
["until"] = &sim_t::interactive_until
;
62 funcs
["while"] = &sim_t::interactive_until
;
63 funcs
["q"] = &sim_t::interactive_quit
;
64 funcs
["h"] = &sim_t::interactive_help
;
68 std::cerr
<< ": " << std::flush
;
69 std::string s
= readline(2);
71 std::stringstream
ss(s
);
73 std::vector
<std::string
> args
;
77 set_procs_debug(true);
88 (this->*funcs
[cmd
])(cmd
, args
);
92 ctrlc_pressed
= false;
95 void sim_t::interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
)
98 "Interactive commands:\n"
99 "reg <core> <reg> # Display <reg> in <core>\n"
100 "fregs <core> <reg> # Display single precision <reg> in <core>\n"
101 "fregd <core> <reg> # Display double precision <reg> in <core>\n"
102 "mem <hex addr> # Show contents of physical memory\n"
103 "str <hex addr> # Show NUL-terminated C string\n"
104 "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n"
105 "until pc <core> <val> # Stop when PC in <core> hits <val>\n"
106 "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n"
107 "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n"
108 "while pc <core> <val> # Run while PC in <core> is <val>\n"
109 "while mem <addr> <val> # Run while memory <addr> is <val>\n"
110 "r [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n"
111 "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n"
112 "q # End the simulation\n"
114 "Note: Hitting enter is the same as: run 1\n"
118 void sim_t::interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
)
120 interactive_run(cmd
,args
,true);
123 void sim_t::interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
)
125 interactive_run(cmd
,args
,false);
128 void sim_t::interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
)
130 size_t steps
= args
.size() ? atoll(args
[0].c_str()) : -1;
131 ctrlc_pressed
= false;
132 set_procs_debug(noisy
);
133 for (size_t i
= 0; i
< steps
&& !ctrlc_pressed
&& !htif
->done(); i
++)
137 void sim_t::interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
)
142 reg_t
sim_t::get_pc(const std::vector
<std::string
>& args
)
145 throw trap_illegal_instruction();
147 int p
= atoi(args
[0].c_str());
148 if(p
>= (int)num_cores())
149 throw trap_illegal_instruction();
151 return procs
[p
]->state
.pc
;
154 reg_t
sim_t::get_reg(const std::vector
<std::string
>& args
)
157 throw trap_illegal_instruction();
160 unsigned long p
= strtoul(args
[0].c_str(), &ptr
, 10);
161 if (*ptr
|| p
>= num_cores())
162 throw trap_illegal_instruction();
164 unsigned long r
= std::find(xpr_name
, xpr_name
+ NXPR
, args
[1]) - xpr_name
;
166 r
= strtoul(args
[1].c_str(), &ptr
, 10);
168 #define DECLARE_CSR(name, number) if (args[1] == #name) return procs[p]->get_csr(number);
170 #include "encoding.h"
177 throw trap_illegal_instruction();
179 return procs
[p
]->state
.XPR
[r
];
182 reg_t
sim_t::get_freg(const std::vector
<std::string
>& args
)
185 throw trap_illegal_instruction();
187 int p
= atoi(args
[0].c_str());
188 int r
= std::find(fpr_name
, fpr_name
+ NFPR
, args
[1]) - fpr_name
;
190 r
= atoi(args
[1].c_str());
191 if(p
>= (int)num_cores() || r
>= NFPR
)
192 throw trap_illegal_instruction();
194 return procs
[p
]->state
.FPR
[r
];
197 void sim_t::interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
)
199 fprintf(stderr
, "0x%016" PRIx64
"\n", get_reg(args
));
209 void sim_t::interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
)
212 f
.r
= get_freg(args
);
213 fprintf(stderr
, "%g\n",f
.s
);
216 void sim_t::interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
)
219 f
.r
= get_freg(args
);
220 fprintf(stderr
, "%g\n",f
.d
);
223 reg_t
sim_t::get_mem(const std::vector
<std::string
>& args
)
225 if(args
.size() != 1 && args
.size() != 2)
226 throw trap_illegal_instruction();
228 std::string addr_str
= args
[0];
229 mmu_t
* mmu
= debug_mmu
;
232 int p
= atoi(args
[0].c_str());
233 if(p
>= (int)num_cores())
234 throw trap_illegal_instruction();
235 mmu
= procs
[p
]->get_mmu();
239 reg_t addr
= strtol(addr_str
.c_str(),NULL
,16), val
;
241 addr
= strtoul(addr_str
.c_str(),NULL
,16);
246 val
= mmu
->load_uint64(addr
);
249 val
= mmu
->load_uint32(addr
);
253 val
= mmu
->load_uint16(addr
);
256 val
= mmu
->load_uint8(addr
);
262 void sim_t::interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
)
264 fprintf(stderr
, "0x%016" PRIx64
"\n", get_mem(args
));
267 void sim_t::interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
)
270 throw trap_illegal_instruction();
272 reg_t addr
= strtol(args
[0].c_str(),NULL
,16);
275 while((ch
= debug_mmu
->load_uint8(addr
++)))
281 void sim_t::interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
)
283 bool cmd_until
= cmd
== "until";
288 reg_t val
= strtol(args
[args
.size()-1].c_str(),NULL
,16);
290 val
= strtoul(args
[args
.size()-1].c_str(),NULL
,16);
292 std::vector
<std::string
> args2
;
293 args2
= std::vector
<std::string
>(args
.begin()+1,args
.end()-1);
295 auto func
= args
[0] == "reg" ? &sim_t::get_reg
:
296 args
[0] == "pc" ? &sim_t::get_pc
:
297 args
[0] == "mem" ? &sim_t::get_mem
:
303 ctrlc_pressed
= false;
309 reg_t current
= (this->*func
)(args2
);
311 if (cmd_until
== (current
== val
))
318 set_procs_debug(false);