51f40610c02f9196a57c4fceb04c9e30f7888048
1 // See LICENSE for license details.
10 #include "gdbserver.h"
23 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
25 : debug(false), sim(sim
), ext(NULL
), id(id
), halt_on_reset(halt_on_reset
)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
31 disassembler
= new disassembler_t(max_xlen
);
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa
|= 1L << ('u' - 'a'); // advertise support for user mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 // advertise support for supervisor and user modes
110 isa
|= 1L << ('s' - 'a');
111 isa
|= 1L << ('u' - 'a');
114 void state_t::reset()
116 memset(this, 0, sizeof(*this));
119 mtvec
= DEFAULT_MTVEC
;
120 load_reservation
= -1;
122 for (unsigned int i
= 0; i
< num_triggers
; i
++) {
123 mcontrol
[i
].type
= 2;
124 mcontrol
[i
].action
= ACTION_NONE
;
129 void processor_t::set_debug(bool value
)
133 ext
->set_debug(value
);
136 void processor_t::set_histogram(bool value
)
138 histogram_enabled
= value
;
139 #ifndef RISCV_ENABLE_HISTOGRAM
141 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
142 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
147 void processor_t::reset()
150 state
.dcsr
.halt
= halt_on_reset
;
151 halt_on_reset
= false;
152 set_csr(CSR_MSTATUS
, state
.mstatus
);
155 ext
->reset(); // reset the extension
158 void processor_t::raise_interrupt(reg_t which
)
160 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
163 // Count number of contiguous 0 bits starting from the LSB.
164 static int ctz(reg_t val
)
168 while ((val
& 1) == 0)
173 void processor_t::take_interrupt()
175 reg_t pending_interrupts
= state
.mip
& state
.mie
;
177 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
178 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
179 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
181 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
182 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
183 enabled_interrupts
|= pending_interrupts
& state
.mideleg
& -s_enabled
;
185 if (enabled_interrupts
)
186 raise_interrupt(ctz(enabled_interrupts
));
189 void processor_t::set_privilege(reg_t prv
)
191 assert(prv
<= PRV_M
);
198 void processor_t::enter_debug_mode(uint8_t cause
)
200 state
.dcsr
.cause
= cause
;
201 state
.dcsr
.prv
= state
.prv
;
202 set_privilege(PRV_M
);
203 state
.dpc
= state
.pc
;
204 state
.pc
= DEBUG_ROM_START
;
205 //debug = true; // TODO
209 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
212 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
215 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
219 if (t
.cause() == CAUSE_BREAKPOINT
&& (
220 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
221 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
222 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
223 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
224 enter_debug_mode(DCSR_CAUSE_SWBP
);
228 if (state
.dcsr
.cause
) {
229 state
.pc
= DEBUG_ROM_EXCEPTION
;
233 // by default, trap to M-mode, unless delegated to S-mode
234 reg_t bit
= t
.cause();
235 reg_t deleg
= state
.medeleg
;
236 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
237 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
238 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
239 // handle the trap in S-mode
240 state
.pc
= state
.stvec
;
241 state
.scause
= t
.cause();
244 state
.sbadaddr
= t
.get_badaddr();
246 reg_t s
= state
.mstatus
;
247 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
248 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
249 s
= set_field(s
, MSTATUS_SIE
, 0);
250 set_csr(CSR_MSTATUS
, s
);
251 set_privilege(PRV_S
);
253 state
.pc
= state
.mtvec
;
255 state
.mcause
= t
.cause();
257 state
.mbadaddr
= t
.get_badaddr();
259 reg_t s
= state
.mstatus
;
260 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
261 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
262 s
= set_field(s
, MSTATUS_MIE
, 0);
263 set_csr(CSR_MSTATUS
, s
);
264 set_privilege(PRV_M
);
267 yield_load_reservation();
270 void processor_t::disasm(insn_t insn
)
272 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
273 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
274 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
277 static bool validate_vm(int max_xlen
, reg_t vm
)
279 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
281 if (max_xlen
== 32 && vm
== VM_SV32
)
283 return vm
== VM_MBARE
;
286 int processor_t::paddr_bits()
288 assert(xlen
== max_xlen
);
289 return max_xlen
== 64 ? 50 : 34;
292 void processor_t::set_csr(int which
, reg_t val
)
294 val
= zext_xlen(val
);
295 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
296 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
301 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
305 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
309 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
310 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
313 if ((val
^ state
.mstatus
) &
314 (MSTATUS_VM
| MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
| MSTATUS_MXR
))
317 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
318 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
319 | MSTATUS_MPP
| MSTATUS_MXR
| (ext
? MSTATUS_XS
: 0);
321 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
324 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
326 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
327 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
329 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
331 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
333 // spike supports the notion of xlen < max_xlen, but current priv spec
334 // doesn't provide a mechanism to run RV32 software on an RV64 machine
339 reg_t mask
= MIP_SSIP
| MIP_STIP
;
340 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
344 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
347 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
351 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
352 #include "encoding.h"
354 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
357 case CSR_MUCOUNTEREN
:
358 state
.mucounteren
= val
& 7;
360 case CSR_MSCOUNTEREN
:
361 state
.mscounteren
= val
& 7;
364 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
365 | SSTATUS_XS
| SSTATUS_PUM
;
366 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
369 return set_csr(CSR_MIP
,
370 (state
.mip
& ~state
.mideleg
) | (val
& state
.mideleg
));
372 return set_csr(CSR_MIE
,
373 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
375 // upper bits of sptbr are the ASID; we only support ASID = 0
376 state
.sptbr
= val
& (((reg_t
)1 << (paddr_bits() - PGSHIFT
)) - 1);
379 case CSR_SEPC
: state
.sepc
= val
; break;
380 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
381 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
382 case CSR_SCAUSE
: state
.scause
= val
; break;
383 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
384 case CSR_MEPC
: state
.mepc
= val
; break;
385 case CSR_MTVEC
: state
.mtvec
= val
>> 2 << 2; break;
386 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
387 case CSR_MCAUSE
: state
.mcause
= val
; break;
388 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
389 case CSR_TSELECT
: state
.tselect
= val
; break;
391 if (state
.tselect
< state
.num_triggers
) {
392 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
393 mc
->select
= get_field(val
, MCONTROL_SELECT
);
394 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
395 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
396 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
397 mc
->m
= get_field(val
, MCONTROL_M
);
398 mc
->h
= get_field(val
, MCONTROL_H
);
399 mc
->s
= get_field(val
, MCONTROL_S
);
400 mc
->u
= get_field(val
, MCONTROL_U
);
401 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
402 mc
->store
= get_field(val
, MCONTROL_STORE
);
403 mc
->load
= get_field(val
, MCONTROL_LOAD
);
404 // Assume we're here because of csrw.
409 if (state
.tselect
< state
.num_triggers
) {
410 state
.tdata1
[state
.tselect
] = val
;
414 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
415 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
416 // TODO: ndreset and fullreset
417 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
418 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
419 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
420 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
421 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
427 state
.dscratch
= val
;
432 reg_t
processor_t::get_csr(int which
)
438 if (!supports_extension('F'))
443 if (!supports_extension('F'))
448 if (!supports_extension('F'))
450 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
454 if ((state
.mucounteren
>> (which
& (xlen
-1))) & 1)
455 return get_csr(which
+ (CSR_MCYCLE
- CSR_CYCLE
));
460 if ((state
.mscounteren
>> (which
& (xlen
-1))) & 1)
461 return get_csr(which
+ (CSR_MCYCLE
- CSR_SCYCLE
));
463 case CSR_MUCOUNTEREN
: return state
.mucounteren
;
464 case CSR_MSCOUNTEREN
: return state
.mscounteren
;
465 case CSR_MUCYCLE_DELTA
: return 0;
466 case CSR_MUTIME_DELTA
: return 0;
467 case CSR_MUINSTRET_DELTA
: return 0;
468 case CSR_MSCYCLE_DELTA
: return 0;
469 case CSR_MSTIME_DELTA
: return 0;
470 case CSR_MSINSTRET_DELTA
: return 0;
471 case CSR_MUCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
472 case CSR_MUTIME_DELTAH
: if (xlen
> 32) break; else return 0;
473 case CSR_MUINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
474 case CSR_MSCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
475 case CSR_MSTIME_DELTAH
: if (xlen
> 32) break; else return 0;
476 case CSR_MSINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
477 case CSR_MCYCLE
: return state
.minstret
;
478 case CSR_MINSTRET
: return state
.minstret
;
479 case CSR_MCYCLEH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
480 case CSR_MINSTRETH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
482 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
483 | SSTATUS_XS
| SSTATUS_PUM
;
484 reg_t sstatus
= state
.mstatus
& mask
;
485 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
486 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
487 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
490 case CSR_SIP
: return state
.mip
& state
.mideleg
;
491 case CSR_SIE
: return state
.mie
& state
.mideleg
;
492 case CSR_SEPC
: return state
.sepc
;
493 case CSR_SBADADDR
: return state
.sbadaddr
;
494 case CSR_STVEC
: return state
.stvec
;
497 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
499 case CSR_SPTBR
: return state
.sptbr
;
500 case CSR_SSCRATCH
: return state
.sscratch
;
501 case CSR_MSTATUS
: return state
.mstatus
;
502 case CSR_MIP
: return state
.mip
;
503 case CSR_MIE
: return state
.mie
;
504 case CSR_MEPC
: return state
.mepc
;
505 case CSR_MSCRATCH
: return state
.mscratch
;
506 case CSR_MCAUSE
: return state
.mcause
;
507 case CSR_MBADADDR
: return state
.mbadaddr
;
508 case CSR_MISA
: return isa
;
509 case CSR_MARCHID
: return 0;
510 case CSR_MIMPID
: return 0;
511 case CSR_MVENDORID
: return 0;
512 case CSR_MHARTID
: return id
;
513 case CSR_MTVEC
: return state
.mtvec
;
514 case CSR_MEDELEG
: return state
.medeleg
;
515 case CSR_MIDELEG
: return state
.mideleg
;
516 case CSR_TSELECT
: return state
.tselect
;
518 if (state
.tselect
< state
.num_triggers
) {
520 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
521 v
= set_field(v
, 0xfL
<< (xlen
-4), mc
->type
);
522 v
= set_field(v
, 0x3fL
<< (xlen
-10), mc
->maskmax
);
523 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
524 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
525 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
526 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
527 v
= set_field(v
, MCONTROL_M
, mc
->m
);
528 v
= set_field(v
, MCONTROL_H
, mc
->h
);
529 v
= set_field(v
, MCONTROL_S
, mc
->s
);
530 v
= set_field(v
, MCONTROL_U
, mc
->u
);
531 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
532 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
533 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
540 if (state
.tselect
< state
.num_triggers
) {
541 return state
.tdata1
[state
.tselect
];
549 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
550 v
= set_field(v
, DCSR_NDRESET
, 0);
551 v
= set_field(v
, DCSR_FULLRESET
, 0);
552 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
553 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
554 v
= set_field(v
, DCSR_DEBUGINT
, sim
->debug_module
.get_interrupt(id
));
555 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
556 v
= set_field(v
, DCSR_STOPTIME
, 0);
557 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
558 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
559 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
560 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
561 v
= set_field(v
, DCSR_HALT
, state
.dcsr
.halt
);
562 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
568 return state
.dscratch
;
570 throw trap_illegal_instruction();
573 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
575 throw trap_illegal_instruction();
578 insn_func_t
processor_t::decode_insn(insn_t insn
)
580 // look up opcode in hash table
581 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
582 insn_desc_t desc
= opcode_cache
[idx
];
584 if (unlikely(insn
.bits() != desc
.match
)) {
585 // fall back to linear search
586 insn_desc_t
* p
= &instructions
[0];
587 while ((insn
.bits() & p
->mask
) != p
->match
)
591 if (p
->mask
!= 0 && p
> &instructions
[0]) {
592 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
593 // move to front of opcode list to reduce miss penalty
594 while (--p
>= &instructions
[0])
596 instructions
[0] = desc
;
600 opcode_cache
[idx
] = desc
;
601 opcode_cache
[idx
].match
= insn
.bits();
604 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
607 void processor_t::register_insn(insn_desc_t desc
)
609 instructions
.push_back(desc
);
612 void processor_t::build_opcode_map()
615 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
616 if (lhs
.match
== rhs
.match
)
617 return lhs
.mask
> rhs
.mask
;
618 return lhs
.match
> rhs
.match
;
621 std::sort(instructions
.begin(), instructions
.end(), cmp());
623 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
624 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
627 void processor_t::register_extension(extension_t
* x
)
629 for (auto insn
: x
->get_instructions())
632 for (auto disasm_insn
: x
->get_disasms())
633 disassembler
->add_insn(disasm_insn
);
635 throw std::logic_error("only one extension may be registered");
637 x
->set_processor(this);
640 void processor_t::register_base_instructions()
642 #define DECLARE_INSN(name, match, mask) \
643 insn_bits_t name##_match = (match), name##_mask = (mask);
644 #include "encoding.h"
647 #define DEFINE_INSN(name) \
648 REGISTER_INSN(this, name, name##_match, name##_mask)
649 #include "insn_list.h"
652 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
656 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
661 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
666 state
.mip
&= ~MIP_MSIP
;
668 state
.mip
|= MIP_MSIP
;
676 void processor_t::trigger_updated()
679 mmu
->check_triggers_fetch
= false;
680 mmu
->check_triggers_load
= false;
681 mmu
->check_triggers_store
= false;
683 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
684 if (state
.mcontrol
[i
].action
== ACTION_NONE
)
686 if (state
.mcontrol
[i
].execute
) {
687 mmu
->check_triggers_fetch
= true;
689 if (state
.mcontrol
[i
].load
) {
690 mmu
->check_triggers_load
= true;
692 if (state
.mcontrol
[i
].store
) {
693 mmu
->check_triggers_store
= true;