riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "disasm.h"
   9 #include <cinttypes>
  10 #include <cmath>
  11 #include <cstdlib>
  12 #include <iostream>
  13 #include <assert.h>
  14 #include <limits.h>
  15 #include <stdexcept>
  16
  17 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  18   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), run(false), debug(false),
  19     opcode_bits(0)
  20 {
  21   reset(true);
  22   mmu->set_processor(this);
  23
  24   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  25   #include "encoding.h"
  26   #undef DECLARE_INSN
  27 }
  28
  29 processor_t::~processor_t()
  30 {
  31 }
  32
  33 void state_t::reset()
  34 {
  35   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  36   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  37   // and virtual memory disabled.
  38   sr = SR_S;
  39 #ifdef RISCV_ENABLE_64BIT
  40   sr |= SR_S64;
  41 #endif
  42   pc = 0x2000;
  43
  44   // the following state is undefined upon boot-up,
  45   // but we zero it for determinism
  46   XPR.reset();
  47   FPR.reset();
  48
  49   evec = 0;
  50   epc = 0;
  51   badvaddr = 0;
  52   cause = 0;
  53   pcr_k0 = 0;
  54   pcr_k1 = 0;
  55   count = 0;
  56   compare = 0;
  57   fflags = 0;
  58   frm = 0;
  59
  60   load_reservation = -1;
  61 }
  62
  63 void processor_t::set_debug(bool value)
  64 {
  65   debug = value;
  66   if (ext)
  67     ext->set_debug(value);
  68 }
  69
  70 void processor_t::reset(bool value)
  71 {
  72   if (run == !value)
  73     return;
  74   run = !value;
  75
  76   state.reset(); // reset the core
  77   if (ext)
  78     ext->reset(); // reset the extension
  79 }
  80
  81 void processor_t::take_interrupt()
  82 {
  83   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  84   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  85
  86   if (interrupts && (state.sr & SR_EI))
  87     for (int i = 0; ; i++, interrupts >>= 1)
  88       if (interrupts & 1)
  89         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  90 }
  91
  92 void processor_t::step(size_t n)
  93 {
  94   if(!run)
  95     return;
  96
  97   size_t i = 0;
  98   reg_t npc = state.pc;
  99   mmu_t* _mmu = mmu;
 100
 101   try
 102   {
 103     take_interrupt();
 104
 105     // execute_insn fetches and executes one instruction
 106     #define execute_insn(noisy) \
 107       do { \
 108         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 109         if(noisy) disasm(fetch.insn.insn); \
 110         npc = fetch.func(this, fetch.insn.insn, npc); \
 111       } while(0)
 112
 113
 114     // special execute_insn  for commit log dumping
 115 #ifdef RISCV_ENABLE_COMMITLOG
 116     //static disassembler disasmblr;
 117     #undef execute_insn
 118     #define execute_insn(noisy) \
 119       do { \
 120         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 121         if(noisy) disasm(fetch.insn.insn); \
 122         bool in_spvr = state.sr & SR_S; \
 123         if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
 124         /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
 125         npc = fetch.func(this, fetch.insn.insn, npc); \
 126       } while(0)
 127 #endif
 128
 129     if(debug) for( ; i < n; i++) // print out instructions as we go
 130       execute_insn(true);
 131     else
 132     {
 133       // unrolled for speed
 134       for( ; n > 3 && i < n-3; i+=4)
 135       {
 136         execute_insn(false);
 137         execute_insn(false);
 138         execute_insn(false);
 139         execute_insn(false);
 140       }
 141       for( ; i < n; i++)
 142         execute_insn(false);
 143     }
 144
 145     state.pc = npc;
 146   }
 147   catch(trap_t& t)
 148   {
 149     take_trap(npc, t);
 150   }
 151
 152   // update timer and possibly register a timer interrupt
 153   uint32_t old_count = state.count;
 154   state.count += i;
 155   if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
 156     set_interrupt(IRQ_TIMER, true);
 157 }
 158
 159 void processor_t::take_trap(reg_t pc, trap_t& t)
 160 {
 161   if (debug)
 162     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 163             id, t.name(), pc);
 164
 165   // switch to supervisor, set previous supervisor bit, disable interrupts
 166   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 167                       ((state.sr & SR_S) ? SR_PS : 0) |
 168                       ((state.sr & SR_EI) ? SR_PEI : 0));
 169
 170   yield_load_reservation();
 171   state.cause = t.cause();
 172   state.epc = pc;
 173   state.pc = state.evec;
 174
 175   t.side_effects(&state); // might set badvaddr etc.
 176 }
 177
 178 void processor_t::deliver_ipi()
 179 {
 180   if (run)
 181     set_pcr(CSR_CLEAR_IPI, 1);
 182 }
 183
 184 void processor_t::disasm(insn_t insn)
 185 {
 186   // the disassembler is stateless, so we share it
 187   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 188           id, state.pc, insn.bits(), disassembler.disassemble(insn).c_str());
 189 }
 190
 191 reg_t processor_t::set_pcr(int which, reg_t val)
 192 {
 193   reg_t old_pcr = get_pcr(which);
 194
 195   switch (which)
 196   {
 197     case CSR_FFLAGS:
 198       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 199       break;
 200     case CSR_FRM:
 201       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 202       break;
 203     case CSR_FCSR:
 204       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 205       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 206       break;
 207     case CSR_STATUS:
 208       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 209 #ifndef RISCV_ENABLE_64BIT
 210       state.sr &= ~(SR_S64 | SR_U64);
 211 #endif
 212 #ifndef RISCV_ENABLE_FPU
 213       state.sr &= ~SR_EF;
 214 #endif
 215       if (!ext)
 216         state.sr &= ~SR_EA;
 217       state.sr &= ~SR_ZERO;
 218       mmu->flush_tlb();
 219       break;
 220     case CSR_EPC:
 221       state.epc = val;
 222       break;
 223     case CSR_EVEC:
 224       state.evec = val;
 225       break;
 226     case CSR_CYCLE:
 227     case CSR_TIME:
 228     case CSR_INSTRET:
 229     case CSR_COUNT:
 230       state.count = val;
 231       break;
 232     case CSR_COMPARE:
 233       set_interrupt(IRQ_TIMER, false);
 234       state.compare = val;
 235       break;
 236     case CSR_PTBR:
 237       state.ptbr = val & ~(PGSIZE-1);
 238       break;
 239     case CSR_SEND_IPI:
 240       sim->send_ipi(val);
 241       break;
 242     case CSR_CLEAR_IPI:
 243       set_interrupt(IRQ_IPI, val & 1);
 244       break;
 245     case CSR_SUP0:
 246       state.pcr_k0 = val;
 247       break;
 248     case CSR_SUP1:
 249       state.pcr_k1 = val;
 250       break;
 251     case CSR_TOHOST:
 252       if (state.tohost == 0)
 253         state.tohost = val;
 254       break;
 255     case CSR_FROMHOST:
 256       set_interrupt(IRQ_HOST, val != 0);
 257       state.fromhost = val;
 258       break;
 259   }
 260
 261   return old_pcr;
 262 }
 263
 264 reg_t processor_t::get_pcr(int which)
 265 {
 266   switch (which)
 267   {
 268     case CSR_FFLAGS:
 269       return state.fflags;
 270     case CSR_FRM:
 271       return state.frm;
 272     case CSR_FCSR:
 273       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 274     case CSR_STATUS:
 275       return state.sr;
 276     case CSR_EPC:
 277       return state.epc;
 278     case CSR_BADVADDR:
 279       return state.badvaddr;
 280     case CSR_EVEC:
 281       return state.evec;
 282     case CSR_CYCLE:
 283     case CSR_TIME:
 284     case CSR_INSTRET:
 285     case CSR_COUNT:
 286       return state.count;
 287     case CSR_COMPARE:
 288       return state.compare;
 289     case CSR_CAUSE:
 290       return state.cause;
 291     case CSR_PTBR:
 292       return state.ptbr;
 293     case CSR_ASID:
 294       return 0;
 295     case CSR_FATC:
 296       mmu->flush_tlb();
 297       return 0;
 298     case CSR_HARTID:
 299       return id;
 300     case CSR_IMPL:
 301       return 1;
 302     case CSR_SUP0:
 303       return state.pcr_k0;
 304     case CSR_SUP1:
 305       return state.pcr_k1;
 306     case CSR_TOHOST:
 307       return state.tohost;
 308     case CSR_FROMHOST:
 309       return state.fromhost;
 310     default:
 311       return -1;
 312   }
 313 }
 314
 315 void processor_t::set_interrupt(int which, bool on)
 316 {
 317   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 318   if (on)
 319     state.sr |= mask;
 320   else
 321     state.sr &= ~mask;
 322 }
 323
 324 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 325 {
 326   throw trap_illegal_instruction();
 327 }
 328
 329 insn_func_t processor_t::decode_insn(insn_t insn)
 330 {
 331   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 332
 333   auto key = insn.bits() & ((1L << opcode_bits)-1);
 334   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 335     if ((insn.bits() & it->second.mask) == it->second.match)
 336       return rv64 ? it->second.rv64 : it->second.rv32;
 337
 338   return &illegal_instruction;
 339 }
 340
 341 void processor_t::register_insn(insn_desc_t desc)
 342 {
 343   assert(desc.mask & 1);
 344   if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 345   {
 346     unsigned x = 0;
 347     while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 348            (opcode_bits == 0 || x <= opcode_bits))
 349       x++;
 350     opcode_bits = x;
 351
 352     decltype(opcode_map) new_map;
 353     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 354       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 355     opcode_map = new_map;
 356   }
 357
 358   opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
 359 }
 360
 361 void processor_t::register_extension(extension_t* x)
 362 {
 363   for (auto insn : x->get_instructions())
 364     register_insn(insn);
 365   for (auto disasm_insn : x->get_disasms())
 366     disassembler.add_insn(disasm_insn);
 367   if (ext != NULL)
 368     throw std::logic_error("only one extension may be registered");
 369   ext = x;
 370   x->set_processor(this);
 371 }