6368c8f18cc5ad3f3423894927c06043626cb6af
1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
)
23 : sim(sim
), ext(NULL
), disassembler(new disassembler_t
),
24 id(id
), run(false), debug(false)
26 parse_isa_string(isa
);
28 mmu
= new mmu_t(sim
->mem
, sim
->memsz
);
29 mmu
->set_processor(this);
33 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
39 processor_t::~processor_t()
41 #ifdef RISCV_ENABLE_HISTOGRAM
42 if (histogram_enabled
)
44 fprintf(stderr
, "PC Histogram size:%lu\n", pc_histogram
.size());
45 for(auto iterator
= pc_histogram
.begin(); iterator
!= pc_histogram
.end(); ++iterator
) {
46 fprintf(stderr
, "%0lx %lu\n", (iterator
->first
<< 2), iterator
->second
);
55 static void bad_isa_string(const char* isa
)
57 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
61 void processor_t::parse_isa_string(const char* isa
)
64 const char* all_subsets
= "IMAFDC";
67 cpuid
= reg_t(2) << 62;
69 if (strncmp(p
, "RV32", 4) == 0)
70 max_xlen
= 32, cpuid
= 0, p
+= 4;
71 else if (strncmp(p
, "RV64", 4) == 0)
73 else if (strncmp(p
, "RV", 2) == 0)
76 cpuid
|= 1L << ('S' - 'A'); // advertise support for supervisor mode
84 cpuid
|= 1L << (*p
- 'A');
86 if (auto next
= strchr(all_subsets
, *p
)) {
87 all_subsets
= next
+ 1;
89 } else if (*p
== 'X') {
90 const char* ext
= p
+1, *end
= ext
;
93 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
100 if (supports_extension('D') && !supports_extension('F'))
104 void state_t::reset()
106 memset(this, 0, sizeof(*this));
107 mstatus
= set_field(mstatus
, MSTATUS_PRV
, PRV_M
);
108 mstatus
= set_field(mstatus
, MSTATUS_PRV1
, PRV_S
);
109 mstatus
= set_field(mstatus
, MSTATUS_PRV2
, PRV_S
);
110 pc
= DEFAULT_MTVEC
+ 0x100;
111 load_reservation
= -1;
114 void processor_t::set_debug(bool value
)
118 ext
->set_debug(value
);
121 void processor_t::set_histogram(bool value
)
123 histogram_enabled
= value
;
126 void processor_t::reset(bool value
)
133 set_csr(CSR_MSTATUS
, state
.mstatus
);
136 ext
->reset(); // reset the extension
139 void processor_t::raise_interrupt(reg_t which
)
141 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
144 void processor_t::take_interrupt()
146 int priv
= get_field(state
.mstatus
, MSTATUS_PRV
);
147 int ie
= get_field(state
.mstatus
, MSTATUS_IE
);
148 reg_t interrupts
= state
.mie
& state
.mip
;
150 if (priv
< PRV_M
|| (priv
== PRV_M
&& ie
)) {
151 if (interrupts
& MIP_MSIP
)
152 raise_interrupt(IRQ_SOFT
);
154 if (state
.fromhost
!= 0)
155 raise_interrupt(IRQ_HOST
);
158 if (priv
< PRV_S
|| (priv
== PRV_S
&& ie
)) {
159 if (interrupts
& MIP_SSIP
)
160 raise_interrupt(IRQ_SOFT
);
162 if (interrupts
& MIP_STIP
)
163 raise_interrupt(IRQ_TIMER
);
167 static void commit_log(state_t
* state
, reg_t pc
, insn_t insn
)
169 #ifdef RISCV_ENABLE_COMMITLOG
170 if (get_field(state
->mstatus
, MSTATUS_IE
)) {
171 uint64_t mask
= (insn
.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn
.length() * 8))) - 1;
172 if (state
->log_reg_write
.addr
) {
173 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
") %c%2" PRIu64
" 0x%016" PRIx64
"\n",
176 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
177 state
->log_reg_write
.addr
>> 1,
178 state
->log_reg_write
.data
);
180 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
")\n", pc
, insn
.bits() & mask
);
183 state
->log_reg_write
.addr
= 0;
187 inline void processor_t::update_histogram(size_t pc
)
189 #ifdef RISCV_ENABLE_HISTOGRAM
190 size_t idx
= pc
>> 2;
195 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
197 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
198 if (npc
!= PC_SERIALIZE
) {
199 commit_log(p
->get_state(), pc
, fetch
.insn
);
200 p
->update_histogram(pc
);
205 static void update_timer(state_t
* state
, size_t instret
)
207 uint64_t count0
= (uint64_t)(uint32_t)state
->mtime
;
208 state
->mtime
+= instret
;
209 uint64_t before
= count0
- state
->stimecmp
;
210 if (int64_t(before
^ (before
+ instret
)) < 0)
211 state
->mip
|= MIP_STIP
;
214 static size_t next_timer(state_t
* state
)
216 return state
->stimecmp
- (uint32_t)state
->mtime
;
219 void processor_t::step(size_t n
)
225 if (unlikely(!run
|| !n
))
227 n
= std::min(n
, next_timer(&state
) | 1U);
229 #define maybe_serialize() \
230 if (unlikely(pc == PC_SERIALIZE)) { \
232 state.serialized = true; \
244 insn_fetch_t fetch
= mmu
->load_insn(pc
);
245 if (!state
.serialized
)
247 pc
= execute_insn(this, pc
, fetch
);
253 else while (instret
< n
)
255 size_t idx
= _mmu
->icache_index(pc
);
256 auto ic_entry
= _mmu
->access_icache(pc
);
258 #define ICACHE_ACCESS(idx) { \
259 insn_fetch_t fetch = ic_entry->data; \
261 pc = execute_insn(this, pc, fetch); \
262 if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
263 if (unlikely(ic_entry->tag != pc)) break; \
264 if (unlikely(instret+1 == n)) break; \
283 update_timer(&state
, instret
);
285 // tail-recurse if we didn't execute as many instructions as we'd hoped
290 void processor_t::push_privilege_stack()
292 reg_t s
= state
.mstatus
;
293 s
= set_field(s
, MSTATUS_PRV2
, get_field(state
.mstatus
, MSTATUS_PRV1
));
294 s
= set_field(s
, MSTATUS_IE2
, get_field(state
.mstatus
, MSTATUS_IE1
));
295 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV
));
296 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE
));
297 s
= set_field(s
, MSTATUS_PRV
, PRV_M
);
298 s
= set_field(s
, MSTATUS_MPRV
, 0);
299 s
= set_field(s
, MSTATUS_IE
, 0);
300 set_csr(CSR_MSTATUS
, s
);
303 void processor_t::pop_privilege_stack()
305 reg_t s
= state
.mstatus
;
306 s
= set_field(s
, MSTATUS_PRV
, get_field(state
.mstatus
, MSTATUS_PRV1
));
307 s
= set_field(s
, MSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE1
));
308 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV2
));
309 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE2
));
310 s
= set_field(s
, MSTATUS_PRV2
, PRV_U
);
311 s
= set_field(s
, MSTATUS_IE2
, 1);
312 set_csr(CSR_MSTATUS
, s
);
315 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
318 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
321 state
.pc
= DEFAULT_MTVEC
+ 0x40 * get_field(state
.mstatus
, MSTATUS_PRV
);
322 push_privilege_stack();
323 yield_load_reservation();
324 state
.mcause
= t
.cause();
326 t
.side_effects(&state
); // might set badvaddr etc.
329 void processor_t::deliver_ipi()
331 state
.mip
|= MIP_MSIP
;
334 void processor_t::disasm(insn_t insn
)
336 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
337 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
338 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
341 static bool validate_priv(reg_t priv
)
343 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
346 static bool validate_vm(int max_xlen
, reg_t vm
)
348 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
350 if (max_xlen
== 32 && vm
== VM_SV32
)
352 return vm
== VM_MBARE
;
355 void processor_t::set_csr(int which
, reg_t val
)
361 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
365 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
369 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
370 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
379 state
.mtime
= (uint32_t)val
| (state
.mtime
>> 32 << 32);
388 state
.sutime_delta
= (uint32_t)val
| (state
.sutime_delta
>> 32 << 32);
390 state
.sutime_delta
= val
;
396 state
.sutime_delta
= (val
<< 32) | (uint32_t)state
.sutime_delta
;
399 if ((val
^ state
.mstatus
) & (MSTATUS_VM
| MSTATUS_PRV
| MSTATUS_PRV1
| MSTATUS_MPRV
))
402 reg_t mask
= MSTATUS_IE
| MSTATUS_IE1
| MSTATUS_IE2
| MSTATUS_MPRV
403 | MSTATUS_FS
| (ext
? MSTATUS_XS
: 0);
405 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
407 if (validate_priv(get_field(val
, MSTATUS_PRV
)))
409 if (validate_priv(get_field(val
, MSTATUS_PRV1
)))
410 mask
|= MSTATUS_PRV1
;
411 if (validate_priv(get_field(val
, MSTATUS_PRV2
)))
412 mask
|= MSTATUS_PRV2
;
414 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
416 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
417 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
419 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
421 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
423 // spike supports the notion of xlen < max_xlen, but current priv spec
424 // doesn't provide a mechanism to run RV32 software on an RV64 machine
429 reg_t mask
= MIP_SSIP
| MIP_MSIP
;
430 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
434 reg_t mask
= MIP_SSIP
| MIP_MSIP
| MIP_STIP
;
435 state
.mie
= (state
.mie
& ~mask
) | (val
& mask
);
439 reg_t ms
= state
.mstatus
;
440 ms
= set_field(ms
, MSTATUS_IE
, get_field(val
, SSTATUS_IE
));
441 ms
= set_field(ms
, MSTATUS_IE1
, get_field(val
, SSTATUS_PIE
));
442 ms
= set_field(ms
, MSTATUS_PRV1
, get_field(val
, SSTATUS_PS
));
443 ms
= set_field(ms
, MSTATUS_FS
, get_field(val
, SSTATUS_FS
));
444 ms
= set_field(ms
, MSTATUS_XS
, get_field(val
, SSTATUS_XS
));
445 ms
= set_field(ms
, MSTATUS_MPRV
, get_field(val
, SSTATUS_MPRV
));
446 return set_csr(CSR_MSTATUS
, ms
);
449 reg_t mask
= MIP_SSIP
;
450 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
454 reg_t mask
= MIP_SSIP
| MIP_STIP
;
455 state
.mie
= (state
.mie
& ~mask
) | (val
& mask
);
458 case CSR_SEPC
: state
.sepc
= val
; break;
459 case CSR_STVEC
: state
.stvec
= val
& ~3; break;
461 state
.mip
&= ~MIP_STIP
;
462 state
.stimecmp
= val
;
464 case CSR_SPTBR
: state
.sptbr
= zext_xlen(val
& -PGSIZE
); break;
465 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
466 case CSR_MEPC
: state
.mepc
= val
; break;
467 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
468 case CSR_MCAUSE
: state
.mcause
= val
; break;
469 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
470 case CSR_SEND_IPI
: sim
->send_ipi(val
); break;
472 if (state
.tohost
== 0)
475 case CSR_MFROMHOST
: state
.fromhost
= val
; break;
479 reg_t
processor_t::get_csr(int which
)
485 if (!supports_extension('F'))
490 if (!supports_extension('F'))
495 if (!supports_extension('F'))
497 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
503 return state
.mtime
>> 32;
511 return state
.mtime
+ state
.sutime_delta
;
521 return (state
.mtime
+ state
.sutime_delta
) >> 32;
524 ss
= set_field(ss
, SSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE
));
525 ss
= set_field(ss
, SSTATUS_PIE
, get_field(state
.mstatus
, MSTATUS_IE1
));
526 ss
= set_field(ss
, SSTATUS_PS
, get_field(state
.mstatus
, MSTATUS_PRV1
));
527 ss
= set_field(ss
, SSTATUS_FS
, get_field(state
.mstatus
, MSTATUS_FS
));
528 ss
= set_field(ss
, SSTATUS_XS
, get_field(state
.mstatus
, MSTATUS_XS
));
529 ss
= set_field(ss
, SSTATUS_MPRV
, get_field(state
.mstatus
, MSTATUS_MPRV
));
530 if (get_field(state
.mstatus
, MSTATUS64_SD
))
531 ss
= set_field(ss
, (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
), 1);
534 case CSR_SIP
: return state
.mip
& (MIP_SSIP
| MIP_STIP
);
535 case CSR_SIE
: return state
.mie
& (MIP_SSIP
| MIP_STIP
);
536 case CSR_SEPC
: return state
.sepc
;
537 case CSR_SBADADDR
: return state
.sbadaddr
;
538 case CSR_STVEC
: return state
.stvec
;
539 case CSR_STIMECMP
: return state
.stimecmp
;
542 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
544 case CSR_SPTBR
: return state
.sptbr
;
545 case CSR_SASID
: return 0;
546 case CSR_SSCRATCH
: return state
.sscratch
;
547 case CSR_MSTATUS
: return state
.mstatus
;
548 case CSR_MIP
: return state
.mip
;
549 case CSR_MIE
: return state
.mie
;
550 case CSR_MEPC
: return state
.mepc
;
551 case CSR_MSCRATCH
: return state
.mscratch
;
552 case CSR_MCAUSE
: return state
.mcause
;
553 case CSR_MBADADDR
: return state
.mbadaddr
;
554 case CSR_MCPUID
: return cpuid
;
555 case CSR_MIMPID
: return IMPL_ROCKET
;
556 case CSR_MHARTID
: return id
;
557 case CSR_MTVEC
: return DEFAULT_MTVEC
;
558 case CSR_MTDELEG
: return 0;
560 sim
->get_htif()->tick(); // not necessary, but faster
563 sim
->get_htif()->tick(); // not necessary, but faster
564 return state
.fromhost
;
565 case CSR_SEND_IPI
: return 0;
584 throw trap_illegal_instruction();
587 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
589 throw trap_illegal_instruction();
592 insn_func_t
processor_t::decode_insn(insn_t insn
)
594 size_t mask
= opcode_map
.size()-1;
595 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
597 while ((insn
.bits() & desc
->mask
) != desc
->match
)
600 return xlen
== 64 ? desc
->rv64
: desc
->rv32
;
603 void processor_t::register_insn(insn_desc_t desc
)
605 assert(desc
.mask
& 1);
606 instructions
.push_back(desc
);
609 void processor_t::build_opcode_map()
612 for (auto& inst
: instructions
)
613 while ((inst
.mask
& buckets
) != buckets
)
618 decltype(insn_desc_t::match
) mask
;
619 cmp(decltype(mask
) mask
) : mask(mask
) {}
620 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
621 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
622 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
623 return lhs
.match
< rhs
.match
;
626 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
628 opcode_map
.resize(buckets
);
629 opcode_store
.resize(instructions
.size() + 1);
632 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
634 opcode_map
[b
] = &opcode_store
[j
];
635 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
636 opcode_store
[j
++] = instructions
[i
++];
639 assert(j
== opcode_store
.size()-1);
640 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
641 opcode_store
[j
].rv32
= &illegal_instruction
;
642 opcode_store
[j
].rv64
= &illegal_instruction
;
645 void processor_t::register_extension(extension_t
* x
)
647 for (auto insn
: x
->get_instructions())
650 for (auto disasm_insn
: x
->get_disasms())
651 disassembler
->add_insn(disasm_insn
);
653 throw std::logic_error("only one extension may be registered");
655 x
->set_processor(this);