riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121 }
 122
 123 void processor_t::set_debug(bool value)
 124 {
 125   debug = value;
 126   if (ext)
 127     ext->set_debug(value);
 128 }
 129
 130 void processor_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133 #ifndef RISCV_ENABLE_HISTOGRAM
 134   if (value) {
 135     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 136     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 137   }
 138 #endif
 139 }
 140
 141 void processor_t::reset()
 142 {
 143   state.reset();
 144   state.dcsr.halt = halt_on_reset;
 145   halt_on_reset = false;
 146   set_csr(CSR_MSTATUS, state.mstatus);
 147
 148   if (ext)
 149     ext->reset(); // reset the extension
 150 }
 151
 152 void processor_t::raise_interrupt(reg_t which)
 153 {
 154   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 155 }
 156
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt()
 167 {
 168   reg_t pending_interrupts = state.mip & state.mie;
 169
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 177
 178   if (enabled_interrupts)
 179     raise_interrupt(ctz(enabled_interrupts));
 180 }
 181
 182 void processor_t::set_privilege(reg_t prv)
 183 {
 184   assert(prv <= PRV_M);
 185   if (prv == PRV_H)
 186     prv = PRV_U;
 187   mmu->flush_tlb();
 188   state.prv = prv;
 189 }
 190
 191 void processor_t::enter_debug_mode(uint8_t cause)
 192 {
 193   state.dcsr.cause = cause;
 194   state.dcsr.prv = state.prv;
 195   set_privilege(PRV_M);
 196   state.dpc = state.pc;
 197   state.pc = DEBUG_ROM_START;
 198   //debug = true; // TODO
 199 }
 200
 201 void processor_t::take_trap(trap_t& t, reg_t epc)
 202 {
 203   if (debug) {
 204     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 205             id, t.name(), epc);
 206     if (t.has_badaddr())
 207       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 208           t.get_badaddr());
 209   }
 210
 211   if (t.cause() == CAUSE_BREAKPOINT && (
 212               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 213               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 214               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 215               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 216     enter_debug_mode(DCSR_CAUSE_SWBP);
 217     return;
 218   }
 219
 220   if (state.dcsr.cause) {
 221     state.pc = DEBUG_ROM_EXCEPTION;
 222     return;
 223   }
 224
 225   // by default, trap to M-mode, unless delegated to S-mode
 226   reg_t bit = t.cause();
 227   reg_t deleg = state.medeleg;
 228   if (bit & ((reg_t)1 << (max_xlen-1)))
 229     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 230   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 231     // handle the trap in S-mode
 232     state.pc = state.stvec;
 233     state.scause = t.cause();
 234     state.sepc = epc;
 235     if (t.has_badaddr())
 236       state.sbadaddr = t.get_badaddr();
 237
 238     reg_t s = state.mstatus;
 239     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 240     s = set_field(s, MSTATUS_SPP, state.prv);
 241     s = set_field(s, MSTATUS_SIE, 0);
 242     set_csr(CSR_MSTATUS, s);
 243     set_privilege(PRV_S);
 244   } else {
 245     state.pc = state.mtvec;
 246     state.mepc = epc;
 247     state.mcause = t.cause();
 248     if (t.has_badaddr())
 249       state.mbadaddr = t.get_badaddr();
 250
 251     reg_t s = state.mstatus;
 252     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 253     s = set_field(s, MSTATUS_MPP, state.prv);
 254     s = set_field(s, MSTATUS_MIE, 0);
 255     set_csr(CSR_MSTATUS, s);
 256     set_privilege(PRV_M);
 257   }
 258
 259   yield_load_reservation();
 260 }
 261
 262 void processor_t::disasm(insn_t insn)
 263 {
 264   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 265   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 266           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 267 }
 268
 269 static bool validate_vm(int max_xlen, reg_t vm)
 270 {
 271   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 272     return true;
 273   if (max_xlen == 32 && vm == VM_SV32)
 274     return true;
 275   return vm == VM_MBARE;
 276 }
 277
 278 int processor_t::paddr_bits()
 279 {
 280   assert(xlen == max_xlen);
 281   return max_xlen == 64 ? 50 : 34;
 282 }
 283
 284 void processor_t::set_csr(int which, reg_t val)
 285 {
 286   val = zext_xlen(val);
 287   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 288   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 289   switch (which)
 290   {
 291     case CSR_FFLAGS:
 292       dirty_fp_state;
 293       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 294       break;
 295     case CSR_FRM:
 296       dirty_fp_state;
 297       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 298       break;
 299     case CSR_FCSR:
 300       dirty_fp_state;
 301       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 302       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 303       break;
 304     case CSR_MSTATUS: {
 305       if ((val ^ state.mstatus) &
 306           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 307         mmu->flush_tlb();
 308
 309       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 310                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 311                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 312
 313       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 314         mask |= MSTATUS_VM;
 315
 316       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 317
 318       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 319       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 320       if (max_xlen == 32)
 321         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 322       else
 323         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 324
 325       // spike supports the notion of xlen < max_xlen, but current priv spec
 326       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 327       xlen = max_xlen;
 328       break;
 329     }
 330     case CSR_MIP: {
 331       reg_t mask = MIP_SSIP | MIP_STIP;
 332       state.mip = (state.mip & ~mask) | (val & mask);
 333       break;
 334     }
 335     case CSR_MIE:
 336       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 337       break;
 338     case CSR_MIDELEG:
 339       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 340       break;
 341     case CSR_MEDELEG: {
 342       reg_t mask = 0;
 343 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 344 #include "encoding.h"
 345 #undef DECLARE_CAUSE
 346       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 347       break;
 348     }
 349     case CSR_MINSTRET:
 350     case CSR_MCYCLE:
 351       if (xlen == 32)
 352         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 353       else
 354         state.minstret = val;
 355       break;
 356     case CSR_MINSTRETH:
 357     case CSR_MCYCLEH:
 358       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 359       break;
 360     case CSR_MUCOUNTEREN:
 361       state.mucounteren = val;
 362       break;
 363     case CSR_MSCOUNTEREN:
 364       state.mscounteren = val;
 365       break;
 366     case CSR_SSTATUS: {
 367       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 368                  | SSTATUS_XS | SSTATUS_PUM;
 369       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 370     }
 371     case CSR_SIP:
 372       return set_csr(CSR_MIP,
 373                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 374     case CSR_SIE:
 375       return set_csr(CSR_MIE,
 376                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 377     case CSR_SPTBR: {
 378       // upper bits of sptbr are the ASID; we only support ASID = 0
 379       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 380       break;
 381     }
 382     case CSR_SEPC: state.sepc = val; break;
 383     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 384     case CSR_SSCRATCH: state.sscratch = val; break;
 385     case CSR_SCAUSE: state.scause = val; break;
 386     case CSR_SBADADDR: state.sbadaddr = val; break;
 387     case CSR_MEPC: state.mepc = val; break;
 388     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 389     case CSR_MSCRATCH: state.mscratch = val; break;
 390     case CSR_MCAUSE: state.mcause = val; break;
 391     case CSR_MBADADDR: state.mbadaddr = val; break;
 392     case CSR_DCSR:
 393       state.dcsr.prv = get_field(val, DCSR_PRV);
 394       state.dcsr.step = get_field(val, DCSR_STEP);
 395       // TODO: ndreset and fullreset
 396       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 397       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 398       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 399       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 400       state.dcsr.halt = get_field(val, DCSR_HALT);
 401       break;
 402     case CSR_DPC:
 403       state.dpc = val;
 404       break;
 405     case CSR_DSCRATCH:
 406       state.dscratch = val;
 407       break;
 408   }
 409 }
 410
 411 reg_t processor_t::get_csr(int which)
 412 {
 413   reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
 414                  state.prv == PRV_S ? state.mscounteren : -1U;
 415   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 416
 417   if (ctr_ok) {
 418     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 419       return 0;
 420     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 421       return 0;
 422   }
 423   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 424     return 0;
 425   if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 426     return 0;
 427   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 428     return 0;
 429
 430   switch (which)
 431   {
 432     case CSR_FFLAGS:
 433       require_fp;
 434       if (!supports_extension('F'))
 435         break;
 436       return state.fflags;
 437     case CSR_FRM:
 438       require_fp;
 439       if (!supports_extension('F'))
 440         break;
 441       return state.frm;
 442     case CSR_FCSR:
 443       require_fp;
 444       if (!supports_extension('F'))
 445         break;
 446       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 447     case CSR_INSTRET:
 448     case CSR_CYCLE:
 449       if (ctr_ok)
 450         return state.minstret;
 451       break;
 452     case CSR_MINSTRET:
 453     case CSR_MCYCLE:
 454       return state.minstret;
 455     case CSR_MINSTRETH:
 456     case CSR_MCYCLEH:
 457       if (xlen == 32)
 458         return state.minstret >> 32;
 459       break;
 460     case CSR_MUCOUNTEREN: return state.mucounteren;
 461     case CSR_MSCOUNTEREN: return state.mscounteren;
 462     case CSR_SSTATUS: {
 463       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 464                  | SSTATUS_XS | SSTATUS_PUM;
 465       reg_t sstatus = state.mstatus & mask;
 466       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 467           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 468         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 469       return sstatus;
 470     }
 471     case CSR_SIP: return state.mip & state.mideleg;
 472     case CSR_SIE: return state.mie & state.mideleg;
 473     case CSR_SEPC: return state.sepc;
 474     case CSR_SBADADDR: return state.sbadaddr;
 475     case CSR_STVEC: return state.stvec;
 476     case CSR_SCAUSE:
 477       if (max_xlen > xlen)
 478         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 479       return state.scause;
 480     case CSR_SPTBR: return state.sptbr;
 481     case CSR_SSCRATCH: return state.sscratch;
 482     case CSR_MSTATUS: return state.mstatus;
 483     case CSR_MIP: return state.mip;
 484     case CSR_MIE: return state.mie;
 485     case CSR_MEPC: return state.mepc;
 486     case CSR_MSCRATCH: return state.mscratch;
 487     case CSR_MCAUSE: return state.mcause;
 488     case CSR_MBADADDR: return state.mbadaddr;
 489     case CSR_MISA: return isa;
 490     case CSR_MARCHID: return 0;
 491     case CSR_MIMPID: return 0;
 492     case CSR_MVENDORID: return 0;
 493     case CSR_MHARTID: return id;
 494     case CSR_MTVEC: return state.mtvec;
 495     case CSR_MEDELEG: return state.medeleg;
 496     case CSR_MIDELEG: return state.mideleg;
 497     case CSR_TSELECT: return 0;
 498     case CSR_TDATA1: return 0;
 499     case CSR_TDATA2: return 0;
 500     case CSR_TDATA3: return 0;
 501     case CSR_DCSR:
 502       {
 503         uint32_t v = 0;
 504         v = set_field(v, DCSR_XDEBUGVER, 1);
 505         v = set_field(v, DCSR_NDRESET, 0);
 506         v = set_field(v, DCSR_FULLRESET, 0);
 507         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 508         v = set_field(v, DCSR_STEP, state.dcsr.step);
 509         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 510         v = set_field(v, DCSR_STOPCYCLE, 0);
 511         v = set_field(v, DCSR_STOPTIME, 0);
 512         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 513         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 514         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 515         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 516         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 517         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 518         return v;
 519       }
 520     case CSR_DPC:
 521       return state.dpc;
 522     case CSR_DSCRATCH:
 523       return state.dscratch;
 524   }
 525   throw trap_illegal_instruction();
 526 }
 527
 528 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 529 {
 530   throw trap_illegal_instruction();
 531 }
 532
 533 insn_func_t processor_t::decode_insn(insn_t insn)
 534 {
 535   // look up opcode in hash table
 536   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 537   insn_desc_t desc = opcode_cache[idx];
 538
 539   if (unlikely(insn.bits() != desc.match)) {
 540     // fall back to linear search
 541     insn_desc_t* p = &instructions[0];
 542     while ((insn.bits() & p->mask) != p->match)
 543       p++;
 544     desc = *p;
 545
 546     if (p->mask != 0 && p > &instructions[0]) {
 547       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 548         // move to front of opcode list to reduce miss penalty
 549         while (--p >= &instructions[0])
 550           *(p+1) = *p;
 551         instructions[0] = desc;
 552       }
 553     }
 554
 555     opcode_cache[idx] = desc;
 556     opcode_cache[idx].match = insn.bits();
 557   }
 558
 559   return xlen == 64 ? desc.rv64 : desc.rv32;
 560 }
 561
 562 void processor_t::register_insn(insn_desc_t desc)
 563 {
 564   instructions.push_back(desc);
 565 }
 566
 567 void processor_t::build_opcode_map()
 568 {
 569   struct cmp {
 570     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 571       if (lhs.match == rhs.match)
 572         return lhs.mask > rhs.mask;
 573       return lhs.match > rhs.match;
 574     }
 575   };
 576   std::sort(instructions.begin(), instructions.end(), cmp());
 577
 578   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 579     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 580 }
 581
 582 void processor_t::register_extension(extension_t* x)
 583 {
 584   for (auto insn : x->get_instructions())
 585     register_insn(insn);
 586   build_opcode_map();
 587   for (auto disasm_insn : x->get_disasms())
 588     disassembler->add_insn(disasm_insn);
 589   if (ext != NULL)
 590     throw std::logic_error("only one extension may be registered");
 591   ext = x;
 592   x->set_processor(this);
 593 }
 594
 595 void processor_t::register_base_instructions()
 596 {
 597   #define DECLARE_INSN(name, match, mask) \
 598     insn_bits_t name##_match = (match), name##_mask = (mask);
 599   #include "encoding.h"
 600   #undef DECLARE_INSN
 601
 602   #define DEFINE_INSN(name) \
 603     REGISTER_INSN(this, name, name##_match, name##_mask)
 604   #include "insn_list.h"
 605   #undef DEFINE_INSN
 606
 607   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 608   build_opcode_map();
 609 }
 610
 611 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 612 {
 613   return false;
 614 }
 615
 616 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 617 {
 618   switch (addr)
 619   {
 620     case 0:
 621       state.mip &= ~MIP_MSIP;
 622       if (bytes[0] & 1)
 623         state.mip |= MIP_MSIP;
 624       return true;
 625
 626     default:
 627       return false;
 628   }
 629 }