riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include "icache.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  21   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  22     id(_id), run(false), debug(false)
  23 {
  24   reset(true);
  25   mmu->set_processor(this);
  26
  27   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  28   #include "encoding.h"
  29   #undef DECLARE_INSN
  30   build_opcode_map();
  31 }
  32
  33 processor_t::~processor_t()
  34 {
  35 }
  36
  37 void state_t::reset()
  38 {
  39   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  40   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  41   // and virtual memory disabled.
  42   sr = SR_S | SR_S64;
  43   pc = 0x2000;
  44
  45   // the following state is undefined upon boot-up,
  46   // but we zero it for determinism
  47   XPR.reset();
  48   FPR.reset();
  49
  50   epc = 0;
  51   badvaddr = 0;
  52   evec = 0;
  53   ptbr = 0;
  54   pcr_k0 = 0;
  55   pcr_k1 = 0;
  56   cause = 0;
  57   tohost = 0;
  58   fromhost = 0;
  59   count = 0;
  60   compare = 0;
  61   fflags = 0;
  62   frm = 0;
  63
  64   load_reservation = -1;
  65 }
  66
  67 void processor_t::set_debug(bool value)
  68 {
  69   debug = value;
  70   if (ext)
  71     ext->set_debug(value);
  72 }
  73
  74 void processor_t::reset(bool value)
  75 {
  76   if (run == !value)
  77     return;
  78   run = !value;
  79
  80   state.reset(); // reset the core
  81   set_pcr(CSR_STATUS, state.sr);
  82
  83   if (ext)
  84     ext->reset(); // reset the extension
  85 }
  86
  87 void processor_t::take_interrupt()
  88 {
  89   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  90   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  91
  92   if (interrupts && (state.sr & SR_EI))
  93     for (int i = 0; ; i++, interrupts >>= 1)
  94       if (interrupts & 1)
  95         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  96 }
  97
  98 static void commit_log(state_t* state, insn_t insn)
  99 {
 100 #ifdef RISCV_ENABLE_COMMITLOG
 101   if (!(state->sr & SR_S))
 102     fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits());
 103 #endif
 104 }
 105
 106 void processor_t::step(size_t n)
 107 {
 108   if(!run)
 109     return;
 110
 111   mmu_t* _mmu = mmu;
 112   auto count32 = decltype(state.compare)(state.count);
 113   bool count_le_compare = count32 <= state.compare;
 114   n = std::min(n, size_t(state.compare - count32) | 1);
 115
 116   try
 117   {
 118     take_interrupt();
 119
 120     if (debug) // print out instructions as we go
 121     {
 122       for (size_t i = 0; i < n; state.count++, i++)
 123       {
 124         insn_fetch_t fetch = mmu->load_insn(state.pc);
 125         disasm(fetch.insn.insn);
 126         commit_log(&state, fetch.insn.insn);
 127         state.pc = fetch.func(this, fetch.insn.insn, state.pc);
 128       }
 129     }
 130     else while (n > 0)
 131     {
 132       size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
 133       auto ic_entry_init = &_mmu->icache[idx], ic_entry = ic_entry_init;
 134
 135       #define update_count() { \
 136         size_t i = ic_entry - ic_entry_init; \
 137         state.count += i; \
 138         if (i >= n) break; \
 139         n -= i; }
 140
 141       #define ICACHE_ACCESS(idx) { \
 142         insn_t insn = ic_entry->data.insn.insn; \
 143         insn_func_t func = ic_entry->data.func; \
 144         if (unlikely(ic_entry->tag != state.pc)) break; \
 145         ic_entry++; \
 146         commit_log(&state, insn); \
 147         state.pc = func(this, insn, state.pc); }
 148
 149       switch (idx) while (true)
 150       {
 151         ICACHE_SWITCH;
 152         update_count();
 153         ic_entry_init = ic_entry = &_mmu->icache[0];
 154       }
 155
 156       _mmu->access_icache(state.pc);
 157       update_count();
 158     }
 159   }
 160   catch(trap_t& t)
 161   {
 162     take_trap(t);
 163   }
 164
 165   bool count_ge_compare =
 166     uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
 167   if (count_le_compare && count_ge_compare)
 168     set_interrupt(IRQ_TIMER, true);
 169 }
 170
 171 void processor_t::take_trap(trap_t& t)
 172 {
 173   if (debug)
 174     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 175             id, t.name(), state.pc);
 176
 177   // switch to supervisor, set previous supervisor bit, disable interrupts
 178   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 179                       ((state.sr & SR_S) ? SR_PS : 0) |
 180                       ((state.sr & SR_EI) ? SR_PEI : 0));
 181
 182   yield_load_reservation();
 183   state.cause = t.cause();
 184   state.epc = state.pc;
 185   state.pc = state.evec;
 186
 187   t.side_effects(&state); // might set badvaddr etc.
 188 }
 189
 190 void processor_t::deliver_ipi()
 191 {
 192   if (run)
 193     set_pcr(CSR_CLEAR_IPI, 1);
 194 }
 195
 196 void processor_t::disasm(insn_t insn)
 197 {
 198   // the disassembler is stateless, so we share it
 199   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 200           id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
 201 }
 202
 203 reg_t processor_t::set_pcr(int which, reg_t val)
 204 {
 205   reg_t old_pcr = get_pcr(which);
 206
 207   switch (which)
 208   {
 209     case CSR_FFLAGS:
 210       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 211       break;
 212     case CSR_FRM:
 213       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 214       break;
 215     case CSR_FCSR:
 216       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 217       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 218       break;
 219     case CSR_STATUS:
 220       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 221 #ifndef RISCV_ENABLE_64BIT
 222       state.sr &= ~(SR_S64 | SR_U64);
 223 #endif
 224 #ifndef RISCV_ENABLE_FPU
 225       state.sr &= ~SR_EF;
 226 #endif
 227       if (!ext)
 228         state.sr &= ~SR_EA;
 229       state.sr &= ~SR_ZERO;
 230       rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 231       mmu->flush_tlb();
 232       break;
 233     case CSR_EPC:
 234       state.epc = val;
 235       break;
 236     case CSR_EVEC:
 237       state.evec = val & ~3;
 238       break;
 239     case CSR_CYCLE:
 240     case CSR_TIME:
 241     case CSR_INSTRET:
 242     case CSR_COUNT:
 243       state.count = val;
 244       break;
 245     case CSR_COMPARE:
 246       set_interrupt(IRQ_TIMER, false);
 247       state.compare = val;
 248       break;
 249     case CSR_PTBR:
 250       state.ptbr = val & ~(PGSIZE-1);
 251       break;
 252     case CSR_SEND_IPI:
 253       sim->send_ipi(val);
 254       break;
 255     case CSR_CLEAR_IPI:
 256       set_interrupt(IRQ_IPI, val & 1);
 257       break;
 258     case CSR_SUP0:
 259       state.pcr_k0 = val;
 260       break;
 261     case CSR_SUP1:
 262       state.pcr_k1 = val;
 263       break;
 264     case CSR_TOHOST:
 265       if (state.tohost == 0)
 266         state.tohost = val;
 267       break;
 268     case CSR_FROMHOST:
 269       set_fromhost(val);
 270       break;
 271   }
 272
 273   return old_pcr;
 274 }
 275
 276 void processor_t::set_fromhost(reg_t val)
 277 {
 278   set_interrupt(IRQ_HOST, val != 0);
 279   state.fromhost = val;
 280 }
 281
 282 reg_t processor_t::get_pcr(int which)
 283 {
 284   switch (which)
 285   {
 286     case CSR_FFLAGS:
 287       return state.fflags;
 288     case CSR_FRM:
 289       return state.frm;
 290     case CSR_FCSR:
 291       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 292     case CSR_STATUS:
 293       return state.sr;
 294     case CSR_EPC:
 295       return state.epc;
 296     case CSR_BADVADDR:
 297       return state.badvaddr;
 298     case CSR_EVEC:
 299       return state.evec;
 300     case CSR_CYCLE:
 301     case CSR_TIME:
 302     case CSR_INSTRET:
 303     case CSR_COUNT:
 304       return state.count;
 305     case CSR_COMPARE:
 306       return state.compare;
 307     case CSR_CAUSE:
 308       return state.cause;
 309     case CSR_PTBR:
 310       return state.ptbr;
 311     case CSR_SEND_IPI:
 312     case CSR_CLEAR_IPI:
 313       return 0;
 314     case CSR_ASID:
 315       return 0;
 316     case CSR_FATC:
 317       mmu->flush_tlb();
 318       return 0;
 319     case CSR_HARTID:
 320       return id;
 321     case CSR_IMPL:
 322       return 1;
 323     case CSR_SUP0:
 324       return state.pcr_k0;
 325     case CSR_SUP1:
 326       return state.pcr_k1;
 327     case CSR_TOHOST:
 328       sim->get_htif()->tick(); // not necessary, but faster
 329       return state.tohost;
 330     case CSR_FROMHOST:
 331       sim->get_htif()->tick(); // not necessary, but faster
 332       return state.fromhost;
 333     default:
 334       throw trap_illegal_instruction();
 335   }
 336 }
 337
 338 void processor_t::set_interrupt(int which, bool on)
 339 {
 340   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 341   if (on)
 342     state.sr |= mask;
 343   else
 344     state.sr &= ~mask;
 345 }
 346
 347 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 348 {
 349   throw trap_illegal_instruction();
 350 }
 351
 352 insn_func_t processor_t::decode_insn(insn_t insn)
 353 {
 354   size_t mask = opcode_map.size()-1;
 355   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 356
 357   while ((insn.bits() & desc->mask) != desc->match)
 358     desc++;
 359
 360   return rv64 ? desc->rv64 : desc->rv32;
 361 }
 362
 363 void processor_t::register_insn(insn_desc_t desc)
 364 {
 365   assert(desc.mask & 1);
 366   instructions.push_back(desc);
 367 }
 368
 369 void processor_t::build_opcode_map()
 370 {
 371   size_t buckets = -1;
 372   for (auto& inst : instructions)
 373     while ((inst.mask & buckets) != buckets)
 374       buckets /= 2;
 375   buckets++;
 376
 377   struct cmp {
 378     decltype(insn_desc_t::match) mask;
 379     cmp(decltype(mask) mask) : mask(mask) {}
 380     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 381       if ((lhs.match & mask) != (rhs.match & mask))
 382         return (lhs.match & mask) < (rhs.match & mask);
 383       return lhs.match < rhs.match;
 384     }
 385   };
 386   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 387
 388   opcode_map.resize(buckets);
 389   opcode_store.resize(instructions.size() + 1);
 390
 391   size_t j = 0;
 392   for (size_t b = 0, i = 0; b < buckets; b++)
 393   {
 394     opcode_map[b] = &opcode_store[j];
 395     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 396       opcode_store[j++] = instructions[i++];
 397   }
 398
 399   assert(j == opcode_store.size()-1);
 400   opcode_store[j].match = opcode_store[j].mask = 0;
 401   opcode_store[j].rv32 = &illegal_instruction;
 402   opcode_store[j].rv64 = &illegal_instruction;
 403 }
 404
 405 void processor_t::register_extension(extension_t* x)
 406 {
 407   for (auto insn : x->get_instructions())
 408     register_insn(insn);
 409   build_opcode_map();
 410   for (auto disasm_insn : x->get_disasms())
 411     disassembler->add_insn(disasm_insn);
 412   if (ext != NULL)
 413     throw std::logic_error("only one extension may be registered");
 414   ext = x;
 415   x->set_processor(this);
 416 }