riscv/processor.cc

   1 #include "processor.h"
   2 #include <bfd.h>
   3 #include <dis-asm.h>
   4 #include <cmath>
   5 #include <cstdlib>
   6 #include <iostream>
   7 #include "common.h"
   8 #include "config.h"
   9 #include "sim.h"
  10 #include "softfloat.h"
  11 #include "platform.h" // softfloat isNaNF32UI, etc.
  12 #include "internals.h" // ditto
  13
  14 processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
  15   : sim(_sim), mmu(_mem,_memsz)
  16 {
  17   memset(XPR,0,sizeof(XPR));
  18   memset(FPR,0,sizeof(FPR));
  19   pc = 0;
  20   evec = 0;
  21   epc = 0;
  22   badvaddr = 0;
  23   cause = 0;
  24   pcr_k0 = 0;
  25   pcr_k1 = 0;
  26   tohost = 0;
  27   fromhost = 0;
  28   count = 0;
  29   compare = 0;
  30   set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
  31   set_fsr(0);
  32
  33   memset(counters,0,sizeof(counters));
  34
  35   // a few assumptions about endianness, including freg_t union
  36   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
  37   static_assert(sizeof(freg_t) == 8);
  38   static_assert(sizeof(reg_t) == 8);
  39
  40   static_assert(sizeof(insn_t) == 4);
  41   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
  42 }
  43
  44 void processor_t::init(uint32_t _id)
  45 {
  46   id = _id;
  47 }
  48
  49 void processor_t::set_sr(uint32_t val)
  50 {
  51   sr = val & ~SR_ZERO;
  52 #ifndef RISCV_ENABLE_64BIT
  53   sr &= ~(SR_SX | SR_UX);
  54 #endif
  55 #ifndef RISCV_ENABLE_FPU
  56   sr &= ~SR_EF;
  57 #endif
  58 #ifndef RISCV_ENABLE_RVC
  59   sr &= ~SR_EC;
  60 #endif
  61
  62   xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
  63 }
  64
  65 void processor_t::set_fsr(uint32_t val)
  66 {
  67   fsr = val & ~FSR_ZERO;
  68 }
  69
  70 void processor_t::step(size_t n, bool noisy)
  71 {
  72   size_t i = 0;
  73   while(1) try
  74   {
  75     for( ; i < n; i++)
  76     {
  77       uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
  78       interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
  79       if(interrupts && (sr & SR_ET))
  80         take_trap(trap_interrupt,noisy);
  81
  82       insn_t insn = mmu.load_insn(pc, sr & SR_EC);
  83
  84       reg_t npc = pc + insn_length(insn);
  85
  86       if(noisy)
  87         disasm(insn,pc);
  88
  89       #include "execute.h"
  90
  91       pc = npc;
  92       XPR[0] = 0;
  93
  94       if(count++ == compare)
  95         cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
  96     }
  97     return;
  98   }
  99   catch(trap_t t)
 100   {
 101     i++;
 102     take_trap(t,noisy);
 103   }
 104 }
 105
 106 void processor_t::take_trap(trap_t t, bool noisy)
 107 {
 108   demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
 109   demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
 110          id, trap_name(t), (unsigned long long)pc);
 111   if(noisy)
 112     printf("core %3d: trap %s, pc 0x%016llx\n",
 113            id, trap_name(t), (unsigned long long)pc);
 114
 115   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 116   cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
 117   epc = pc;
 118   pc = evec;
 119   badvaddr = mmu.get_badvaddr();
 120 }
 121
 122 void processor_t::disasm(insn_t insn, reg_t pc)
 123 {
 124   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
 125
 126   #ifdef RISCV_HAVE_LIBOPCODES
 127   disassemble_info info;
 128   INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
 129   info.flavour = bfd_target_unknown_flavour;
 130   info.arch = bfd_arch_mips;
 131   info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
 132   info.endian = BFD_ENDIAN_LITTLE;
 133   info.buffer = (bfd_byte*)&insn;
 134   info.buffer_length = sizeof(insn);
 135   info.buffer_vma = pc;
 136
 137   demand(print_insn_little_mips(pc, &info) == sizeof(insn), "disasm bug!");
 138   #else
 139   printf("unknown");
 140   #endif
 141   printf("\n");
 142 }