riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  24   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  25     id(id), run(false), debug(false)
  26 {
  27   parse_isa_string(isa);
  28
  29   mmu = new mmu_t(sim, this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   mtvec = DEFAULT_MTVEC;
 119   load_reservation = -1;
 120 }
 121
 122 void processor_t::set_debug(bool value)
 123 {
 124   debug = value;
 125   if (ext)
 126     ext->set_debug(value);
 127 }
 128
 129 void processor_t::set_histogram(bool value)
 130 {
 131   histogram_enabled = value;
 132 #ifndef RISCV_ENABLE_HISTOGRAM
 133   if (value) {
 134     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 135     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 136   }
 137 #endif
 138 }
 139
 140 void processor_t::reset(bool value)
 141 {
 142   if (run == !value)
 143     return;
 144   run = !value;
 145
 146   state.reset();
 147   set_csr(CSR_MSTATUS, state.mstatus);
 148
 149   if (ext)
 150     ext->reset(); // reset the extension
 151 }
 152
 153 void processor_t::raise_interrupt(reg_t which)
 154 {
 155   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 156 }
 157
 158 static int ctz(reg_t val)
 159 {
 160   int res = 0;
 161   if (val)
 162     while ((val & 1) == 0)
 163       val >>= 1, res++;
 164   return res;
 165 }
 166
 167 void processor_t::take_interrupt()
 168 {
 169   reg_t pending_interrupts = state.mip & state.mie;
 170
 171   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 172   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 173   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 174
 175   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 176   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 177   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 178
 179   if (enabled_interrupts)
 180     raise_interrupt(ctz(enabled_interrupts));
 181 }
 182
 183 static bool validate_priv(reg_t priv)
 184 {
 185   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 186 }
 187
 188 void processor_t::set_privilege(reg_t prv)
 189 {
 190   assert(validate_priv(prv));
 191   mmu->flush_tlb();
 192   state.prv = prv;
 193 }
 194
 195 void processor_t::enter_debug_mode(uint8_t cause)
 196 {
 197   state.dcsr.cause = cause;
 198   state.dpc = state.pc;
 199   state.pc = DEBUG_ROM_ENTRY;
 200 }
 201
 202 void processor_t::take_trap(trap_t& t, reg_t epc)
 203 {
 204   if (debug)
 205     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 206             id, t.name(), epc);
 207
 208   if (t.cause() == CAUSE_BREAKPOINT &&
 209           sim->gdbserver && sim->gdbserver->connected()) {
 210     enter_debug_mode(DCSR_CAUSE_SWBP);
 211     return;
 212   }
 213
 214   // by default, trap to M-mode, unless delegated to S-mode
 215   reg_t bit = t.cause();
 216   reg_t deleg = state.medeleg;
 217   if (bit & ((reg_t)1 << (max_xlen-1)))
 218     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 219   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 220     // handle the trap in S-mode
 221     state.pc = state.stvec;
 222     state.scause = t.cause();
 223     state.sepc = epc;
 224     if (t.has_badaddr())
 225       state.sbadaddr = t.get_badaddr();
 226
 227     reg_t s = state.mstatus;
 228     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 229     s = set_field(s, MSTATUS_SPP, state.prv);
 230     s = set_field(s, MSTATUS_SIE, 0);
 231     set_csr(CSR_MSTATUS, s);
 232     set_privilege(PRV_S);
 233   } else {
 234     state.pc = state.mtvec;
 235     state.mcause = t.cause();
 236     state.mepc = epc;
 237     if (t.has_badaddr())
 238       state.mbadaddr = t.get_badaddr();
 239
 240     reg_t s = state.mstatus;
 241     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 242     s = set_field(s, MSTATUS_MPP, state.prv);
 243     s = set_field(s, MSTATUS_MIE, 0);
 244     set_csr(CSR_MSTATUS, s);
 245     set_privilege(PRV_M);
 246   }
 247
 248   yield_load_reservation();
 249 }
 250
 251 void processor_t::disasm(insn_t insn)
 252 {
 253   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 254   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 255           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 256 }
 257
 258 static bool validate_vm(int max_xlen, reg_t vm)
 259 {
 260   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 261     return true;
 262   if (max_xlen == 32 && vm == VM_SV32)
 263     return true;
 264   return vm == VM_MBARE;
 265 }
 266
 267 void processor_t::set_csr(int which, reg_t val)
 268 {
 269   val = zext_xlen(val);
 270   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 271   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 272   switch (which)
 273   {
 274     case CSR_FFLAGS:
 275       dirty_fp_state;
 276       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 277       break;
 278     case CSR_FRM:
 279       dirty_fp_state;
 280       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 281       break;
 282     case CSR_FCSR:
 283       dirty_fp_state;
 284       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 285       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 286       break;
 287     case CSR_MSTATUS: {
 288       if ((val ^ state.mstatus) &
 289           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 290         mmu->flush_tlb();
 291
 292       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 293                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 294                  | (ext ? MSTATUS_XS : 0);
 295
 296       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 297         mask |= MSTATUS_VM;
 298       if (validate_priv(get_field(val, MSTATUS_MPP)))
 299         mask |= MSTATUS_MPP;
 300
 301       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 302
 303       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 304       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 305       if (max_xlen == 32)
 306         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 307       else
 308         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 309
 310       // spike supports the notion of xlen < max_xlen, but current priv spec
 311       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 312       xlen = max_xlen;
 313       break;
 314     }
 315     case CSR_MIP: {
 316       reg_t mask = MIP_SSIP | MIP_STIP;
 317       state.mip = (state.mip & ~mask) | (val & mask);
 318       break;
 319     }
 320     case CSR_MIE:
 321       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 322       break;
 323     case CSR_MIDELEG:
 324       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 325       break;
 326     case CSR_MEDELEG: {
 327       reg_t mask = 0;
 328 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 329 #include "encoding.h"
 330 #undef DECLARE_CAUSE
 331       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 332       break;
 333     }
 334     case CSR_MUCOUNTEREN:
 335       state.mucounteren = val & 7;
 336       break;
 337     case CSR_MSCOUNTEREN:
 338       state.mscounteren = val & 7;
 339       break;
 340     case CSR_SSTATUS: {
 341       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 342                  | SSTATUS_XS | SSTATUS_PUM;
 343       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 344     }
 345     case CSR_SIP:
 346       return set_csr(CSR_MIP,
 347                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 348     case CSR_SIE:
 349       return set_csr(CSR_MIE,
 350                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 351     case CSR_SEPC: state.sepc = val; break;
 352     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 353     case CSR_SPTBR: state.sptbr = val; break;
 354     case CSR_SSCRATCH: state.sscratch = val; break;
 355     case CSR_SCAUSE: state.scause = val; break;
 356     case CSR_SBADADDR: state.sbadaddr = val; break;
 357     case CSR_MEPC: state.mepc = val; break;
 358     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 359     case CSR_MSCRATCH: state.mscratch = val; break;
 360     case CSR_MCAUSE: state.mcause = val; break;
 361     case CSR_MBADADDR: state.mbadaddr = val; break;
 362     case DCSR_ADDRESS:
 363       state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
 364       state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
 365       // TODO: ndreset and fullreset
 366       state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
 367       state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
 368       state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
 369       state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
 370       state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
 371       break;
 372     case DPC_ADDRESS:
 373       state.dpc = val;
 374       break;
 375     case DSCRATCH_ADDRESS:
 376       state.dscratch = val;
 377       break;
 378   }
 379 }
 380
 381 reg_t processor_t::get_csr(int which)
 382 {
 383   switch (which)
 384   {
 385     case CSR_FFLAGS:
 386       require_fp;
 387       if (!supports_extension('F'))
 388         break;
 389       return state.fflags;
 390     case CSR_FRM:
 391       require_fp;
 392       if (!supports_extension('F'))
 393         break;
 394       return state.frm;
 395     case CSR_FCSR:
 396       require_fp;
 397       if (!supports_extension('F'))
 398         break;
 399       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 400     case CSR_TIME:
 401     case CSR_INSTRET:
 402     case CSR_CYCLE:
 403       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 404         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 405       break;
 406     case CSR_STIME:
 407     case CSR_SINSTRET:
 408     case CSR_SCYCLE:
 409       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 410         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 411       break;
 412     case CSR_MUCOUNTEREN: return state.mucounteren;
 413     case CSR_MSCOUNTEREN: return state.mscounteren;
 414     case CSR_MUCYCLE_DELTA: return 0;
 415     case CSR_MUTIME_DELTA: return 0;
 416     case CSR_MUINSTRET_DELTA: return 0;
 417     case CSR_MSCYCLE_DELTA: return 0;
 418     case CSR_MSTIME_DELTA: return 0;
 419     case CSR_MSINSTRET_DELTA: return 0;
 420     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 421     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 422     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 423     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 424     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 425     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 426     case CSR_MCYCLE: return state.minstret;
 427     case CSR_MINSTRET: return state.minstret;
 428     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 429     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 430     case CSR_SSTATUS: {
 431       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 432                  | SSTATUS_XS | SSTATUS_PUM;
 433       reg_t sstatus = state.mstatus & mask;
 434       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 435           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 436         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 437       return sstatus;
 438     }
 439     case CSR_SIP: return state.mip & state.mideleg;
 440     case CSR_SIE: return state.mie & state.mideleg;
 441     case CSR_SEPC: return state.sepc;
 442     case CSR_SBADADDR: return state.sbadaddr;
 443     case CSR_STVEC: return state.stvec;
 444     case CSR_SCAUSE:
 445       if (max_xlen > xlen)
 446         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 447       return state.scause;
 448     case CSR_SPTBR: return state.sptbr;
 449     case CSR_SASID: return 0;
 450     case CSR_SSCRATCH: return state.sscratch;
 451     case CSR_MSTATUS: return state.mstatus;
 452     case CSR_MIP: return state.mip;
 453     case CSR_MIE: return state.mie;
 454     case CSR_MEPC: return state.mepc;
 455     case CSR_MSCRATCH: return state.mscratch;
 456     case CSR_MCAUSE: return state.mcause;
 457     case CSR_MBADADDR: return state.mbadaddr;
 458     case CSR_MISA: return isa;
 459     case CSR_MARCHID: return 0;
 460     case CSR_MIMPID: return 0;
 461     case CSR_MVENDORID: return 0;
 462     case CSR_MHARTID: return id;
 463     case CSR_MTVEC: return state.mtvec;
 464     case CSR_MEDELEG: return state.medeleg;
 465     case CSR_MIDELEG: return state.mideleg;
 466     case DCSR_ADDRESS:
 467       return
 468           (1 << DCSR_XDEBUGVER_OFFSET) |
 469           (0 << DCSR_HWBPCOUNT_OFFSET) |
 470           (0 << DCSR_NDRESET_OFFSET) |
 471           (0 << DCSR_FULLRESET_OFFSET) |
 472           (state.dcsr.prv << DCSR_PRV_OFFSET) |
 473           (state.dcsr.step << DCSR_STEP_OFFSET) |
 474           (state.dcsr.debugint << DCSR_DEBUGINT_OFFSET) |
 475           (0 << DCSR_STOPCYCLE_OFFSET) |
 476           (0 << DCSR_STOPTIME_OFFSET) |
 477           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
 478           (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
 479           (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
 480           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
 481           (state.dcsr.halt << DCSR_HALT_OFFSET) |
 482           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
 483     case DPC_ADDRESS:
 484       return state.dpc;
 485     case DSCRATCH_ADDRESS:
 486       return state.dscratch;
 487   }
 488   throw trap_illegal_instruction();
 489 }
 490
 491 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 492 {
 493   throw trap_illegal_instruction();
 494 }
 495
 496 insn_func_t processor_t::decode_insn(insn_t insn)
 497 {
 498   // look up opcode in hash table
 499   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 500   insn_desc_t desc = opcode_cache[idx];
 501
 502   if (unlikely(insn.bits() != desc.match)) {
 503     // fall back to linear search
 504     insn_desc_t* p = &instructions[0];
 505     while ((insn.bits() & p->mask) != p->match)
 506       p++;
 507     desc = *p;
 508
 509     if (p->mask != 0 && p > &instructions[0]) {
 510       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 511         // move to front of opcode list to reduce miss penalty
 512         while (--p >= &instructions[0])
 513           *(p+1) = *p;
 514         instructions[0] = desc;
 515       }
 516     }
 517
 518     opcode_cache[idx] = desc;
 519     opcode_cache[idx].match = insn.bits();
 520   }
 521
 522   return xlen == 64 ? desc.rv64 : desc.rv32;
 523 }
 524
 525 void processor_t::register_insn(insn_desc_t desc)
 526 {
 527   instructions.push_back(desc);
 528 }
 529
 530 void processor_t::build_opcode_map()
 531 {
 532   struct cmp {
 533     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 534       if (lhs.match == rhs.match)
 535         return lhs.mask > rhs.mask;
 536       return lhs.match > rhs.match;
 537     }
 538   };
 539   std::sort(instructions.begin(), instructions.end(), cmp());
 540
 541   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 542     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 543 }
 544
 545 void processor_t::register_extension(extension_t* x)
 546 {
 547   for (auto insn : x->get_instructions())
 548     register_insn(insn);
 549   build_opcode_map();
 550   for (auto disasm_insn : x->get_disasms())
 551     disassembler->add_insn(disasm_insn);
 552   if (ext != NULL)
 553     throw std::logic_error("only one extension may be registered");
 554   ext = x;
 555   x->set_processor(this);
 556 }
 557
 558 void processor_t::register_base_instructions()
 559 {
 560   #define DECLARE_INSN(name, match, mask) \
 561     insn_bits_t name##_match = (match), name##_mask = (mask);
 562   #include "encoding.h"
 563   #undef DECLARE_INSN
 564
 565   #define DEFINE_INSN(name) \
 566     REGISTER_INSN(this, name, name##_match, name##_mask)
 567   #include "insn_list.h"
 568   #undef DEFINE_INSN
 569
 570   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 571   build_opcode_map();
 572 }
 573
 574 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 575 {
 576   return false;
 577 }
 578
 579 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 580 {
 581   switch (addr)
 582   {
 583     case 0:
 584       state.mip &= ~MIP_MSIP;
 585       if (bytes[0] & 1)
 586         state.mip |= MIP_MSIP;
 587       return true;
 588
 589     default:
 590       return false;
 591   }
 592 }