riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   // advertise support for supervisor and user modes
 116   isa |= 1L << ('s' - 'a');
 117   isa |= 1L << ('u' - 'a');
 118
 119   max_isa = isa;
 120 }
 121
 122 void state_t::reset()
 123 {
 124   memset(this, 0, sizeof(*this));
 125   prv = PRV_M;
 126   pc = DEFAULT_RSTVEC;
 127   load_reservation = -1;
 128   tselect = 0;
 129   for (unsigned int i = 0; i < num_triggers; i++)
 130     mcontrol[i].type = 2;
 131 }
 132
 133 void processor_t::set_debug(bool value)
 134 {
 135   debug = value;
 136   if (ext)
 137     ext->set_debug(value);
 138 }
 139
 140 void processor_t::set_histogram(bool value)
 141 {
 142   histogram_enabled = value;
 143 #ifndef RISCV_ENABLE_HISTOGRAM
 144   if (value) {
 145     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 146     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 147   }
 148 #endif
 149 }
 150
 151 void processor_t::reset()
 152 {
 153   state.reset();
 154   state.dcsr.halt = halt_on_reset;
 155   halt_on_reset = false;
 156   set_csr(CSR_MSTATUS, state.mstatus);
 157
 158   if (ext)
 159     ext->reset(); // reset the extension
 160 }
 161
 162 // Count number of contiguous 0 bits starting from the LSB.
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt(reg_t pending_interrupts)
 173 {
 174   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 175   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 176   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 177
 178   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 179   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 180   if (enabled_interrupts == 0)
 181     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (state.dcsr.cause == 0 && enabled_interrupts)
 184     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 185 }
 186
 187 static int xlen_to_uxl(int xlen)
 188 {
 189   if (xlen == 32)
 190     return 1;
 191   if (xlen == 64)
 192     return 2;
 193   abort();
 194 }
 195
 196 reg_t processor_t::legalize_privilege(reg_t prv)
 197 {
 198   assert(prv <= PRV_M);
 199
 200   if (!supports_extension('U'))
 201     return PRV_M;
 202
 203   if (prv == PRV_H || !supports_extension('S'))
 204     return PRV_U;
 205
 206   return prv;
 207 }
 208
 209 void processor_t::set_privilege(reg_t prv)
 210 {
 211   mmu->flush_tlb();
 212   state.prv = legalize_privilege(prv);
 213 }
 214
 215 void processor_t::enter_debug_mode(uint8_t cause)
 216 {
 217   state.dcsr.cause = cause;
 218   state.dcsr.prv = state.prv;
 219   set_privilege(PRV_M);
 220   state.dpc = state.pc;
 221   state.pc = DEBUG_ROM_ENTRY;
 222 }
 223
 224 void processor_t::take_trap(trap_t& t, reg_t epc)
 225 {
 226   if (debug) {
 227     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 228             id, t.name(), epc);
 229     if (t.has_badaddr())
 230       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 231           t.get_badaddr());
 232   }
 233
 234   if (state.dcsr.cause) {
 235     if (t.cause() == CAUSE_BREAKPOINT) {
 236       state.pc = DEBUG_ROM_ENTRY;
 237     } else {
 238       state.pc = DEBUG_ROM_TVEC;
 239     }
 240     return;
 241   }
 242
 243   if (t.cause() == CAUSE_BREAKPOINT && (
 244               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 245               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 246               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 247               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 248     enter_debug_mode(DCSR_CAUSE_SWBP);
 249     return;
 250   }
 251
 252   // by default, trap to M-mode, unless delegated to S-mode
 253   reg_t bit = t.cause();
 254   reg_t deleg = state.medeleg;
 255   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 256   if (interrupt)
 257     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 258   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 259     // handle the trap in S-mode
 260     state.pc = state.stvec;
 261     state.scause = t.cause();
 262     state.sepc = epc;
 263     if (t.has_badaddr())
 264       state.sbadaddr = t.get_badaddr();
 265
 266     reg_t s = state.mstatus;
 267     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 268     s = set_field(s, MSTATUS_SPP, state.prv);
 269     s = set_field(s, MSTATUS_SIE, 0);
 270     set_csr(CSR_MSTATUS, s);
 271     set_privilege(PRV_S);
 272   } else {
 273     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 274     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 275     state.mepc = epc;
 276     state.mcause = t.cause();
 277     if (t.has_badaddr())
 278       state.mbadaddr = t.get_badaddr();
 279
 280     reg_t s = state.mstatus;
 281     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 282     s = set_field(s, MSTATUS_MPP, state.prv);
 283     s = set_field(s, MSTATUS_MIE, 0);
 284     set_csr(CSR_MSTATUS, s);
 285     set_privilege(PRV_M);
 286   }
 287
 288   yield_load_reservation();
 289 }
 290
 291 void processor_t::disasm(insn_t insn)
 292 {
 293   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 294   if (last_pc != state.pc || last_bits != bits) {
 295     if (executions != 1) {
 296       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 297     }
 298
 299     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 300             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 301     last_pc = state.pc;
 302     last_bits = bits;
 303     executions = 1;
 304   } else {
 305     executions++;
 306   }
 307 }
 308
 309 int processor_t::paddr_bits()
 310 {
 311   assert(xlen == max_xlen);
 312   return max_xlen == 64 ? 50 : 34;
 313 }
 314
 315 void processor_t::set_csr(int which, reg_t val)
 316 {
 317   val = zext_xlen(val);
 318   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 319   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 320   switch (which)
 321   {
 322     case CSR_FFLAGS:
 323       dirty_fp_state;
 324       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 325       break;
 326     case CSR_FRM:
 327       dirty_fp_state;
 328       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 329       break;
 330     case CSR_FCSR:
 331       dirty_fp_state;
 332       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 333       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 334       break;
 335     case CSR_MSTATUS: {
 336       if ((val ^ state.mstatus) &
 337           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 338         mmu->flush_tlb();
 339
 340       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 341                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 342                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 343                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 344                  (ext ? MSTATUS_XS : 0);
 345
 346       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 347       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 348       if (supports_extension('S'))
 349         mask |= MSTATUS_SPP;
 350
 351       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 352
 353       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 354       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 355       if (max_xlen == 32)
 356         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 357       else
 358         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 359
 360       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 361       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 362       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 363       // U-XLEN == S-XLEN == M-XLEN
 364       xlen = max_xlen;
 365       break;
 366     }
 367     case CSR_MIP: {
 368       reg_t mask = MIP_SSIP | MIP_STIP;
 369       state.mip = (state.mip & ~mask) | (val & mask);
 370       break;
 371     }
 372     case CSR_MIE:
 373       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 374       break;
 375     case CSR_MIDELEG:
 376       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 377       break;
 378     case CSR_MEDELEG: {
 379       reg_t mask =
 380         (1 << CAUSE_MISALIGNED_FETCH) |
 381         (1 << CAUSE_BREAKPOINT) |
 382         (1 << CAUSE_USER_ECALL) |
 383         (1 << CAUSE_FETCH_PAGE_FAULT) |
 384         (1 << CAUSE_LOAD_PAGE_FAULT) |
 385         (1 << CAUSE_STORE_PAGE_FAULT);
 386       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 387       break;
 388     }
 389     case CSR_MINSTRET:
 390     case CSR_MCYCLE:
 391       if (xlen == 32)
 392         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 393       else
 394         state.minstret = val;
 395       break;
 396     case CSR_MINSTRETH:
 397     case CSR_MCYCLEH:
 398       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 399       break;
 400     case CSR_SCOUNTEREN:
 401       state.scounteren = val;
 402       break;
 403     case CSR_MCOUNTEREN:
 404       state.mcounteren = val;
 405       break;
 406     case CSR_SSTATUS: {
 407       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 408                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 409       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 410     }
 411     case CSR_SIP: {
 412       reg_t mask = MIP_SSIP & state.mideleg;
 413       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 414     }
 415     case CSR_SIE:
 416       return set_csr(CSR_MIE,
 417                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 418     case CSR_SPTBR: {
 419       mmu->flush_tlb();
 420       if (max_xlen == 32)
 421         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 422       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 423                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 424                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 425         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 426       break;
 427     }
 428     case CSR_SEPC: state.sepc = val; break;
 429     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 430     case CSR_SSCRATCH: state.sscratch = val; break;
 431     case CSR_SCAUSE: state.scause = val; break;
 432     case CSR_SBADADDR: state.sbadaddr = val; break;
 433     case CSR_MEPC: state.mepc = val; break;
 434     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 435     case CSR_MSCRATCH: state.mscratch = val; break;
 436     case CSR_MCAUSE: state.mcause = val; break;
 437     case CSR_MBADADDR: state.mbadaddr = val; break;
 438     case CSR_MISA: {
 439       if (!(val & (1L << ('F' - 'A'))))
 440         val &= ~(1L << ('D' - 'A'));
 441
 442       // allow MAFDC bits in MISA to be modified
 443       reg_t mask = 0;
 444       mask |= 1L << ('M' - 'A');
 445       mask |= 1L << ('A' - 'A');
 446       mask |= 1L << ('F' - 'A');
 447       mask |= 1L << ('D' - 'A');
 448       mask |= 1L << ('C' - 'A');
 449       mask &= max_isa;
 450
 451       isa = (val & mask) | (isa & ~mask);
 452       break;
 453     }
 454     case CSR_TSELECT:
 455       if (val < state.num_triggers) {
 456         state.tselect = val;
 457       }
 458       break;
 459     case CSR_TDATA1:
 460       {
 461         mcontrol_t *mc = &state.mcontrol[state.tselect];
 462         if (mc->dmode && !state.dcsr.cause) {
 463           break;
 464         }
 465         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 466         mc->select = get_field(val, MCONTROL_SELECT);
 467         mc->timing = get_field(val, MCONTROL_TIMING);
 468         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 469         mc->chain = get_field(val, MCONTROL_CHAIN);
 470         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 471         mc->m = get_field(val, MCONTROL_M);
 472         mc->h = get_field(val, MCONTROL_H);
 473         mc->s = get_field(val, MCONTROL_S);
 474         mc->u = get_field(val, MCONTROL_U);
 475         mc->execute = get_field(val, MCONTROL_EXECUTE);
 476         mc->store = get_field(val, MCONTROL_STORE);
 477         mc->load = get_field(val, MCONTROL_LOAD);
 478         // Assume we're here because of csrw.
 479         if (mc->execute)
 480           mc->timing = 0;
 481         trigger_updated();
 482       }
 483       break;
 484     case CSR_TDATA2:
 485       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 486         break;
 487       }
 488       if (state.tselect < state.num_triggers) {
 489         state.tdata2[state.tselect] = val;
 490       }
 491       break;
 492     case CSR_DCSR:
 493       state.dcsr.prv = get_field(val, DCSR_PRV);
 494       state.dcsr.step = get_field(val, DCSR_STEP);
 495       // TODO: ndreset and fullreset
 496       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 497       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 498       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 499       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 500       state.dcsr.halt = get_field(val, DCSR_HALT);
 501       break;
 502     case CSR_DPC:
 503       state.dpc = val;
 504       break;
 505     case CSR_DSCRATCH:
 506       state.dscratch = val;
 507       break;
 508   }
 509 }
 510
 511 reg_t processor_t::get_csr(int which)
 512 {
 513   uint32_t ctr_en = -1;
 514   if (state.prv < PRV_M)
 515     ctr_en &= state.mcounteren;
 516   if (state.prv < PRV_S)
 517     ctr_en &= state.scounteren;
 518   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 519
 520   if (ctr_ok) {
 521     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 522       return 0;
 523     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 524       return 0;
 525   }
 526   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 527     return 0;
 528   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 529     return 0;
 530   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 531     return 0;
 532
 533   switch (which)
 534   {
 535     case CSR_FFLAGS:
 536       require_fp;
 537       if (!supports_extension('F'))
 538         break;
 539       return state.fflags;
 540     case CSR_FRM:
 541       require_fp;
 542       if (!supports_extension('F'))
 543         break;
 544       return state.frm;
 545     case CSR_FCSR:
 546       require_fp;
 547       if (!supports_extension('F'))
 548         break;
 549       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 550     case CSR_INSTRET:
 551     case CSR_CYCLE:
 552       if (ctr_ok)
 553         return state.minstret;
 554       break;
 555     case CSR_MINSTRET:
 556     case CSR_MCYCLE:
 557       return state.minstret;
 558     case CSR_MINSTRETH:
 559     case CSR_MCYCLEH:
 560       if (xlen == 32)
 561         return state.minstret >> 32;
 562       break;
 563     case CSR_SCOUNTEREN: return state.scounteren;
 564     case CSR_MCOUNTEREN: return state.mcounteren;
 565     case CSR_SSTATUS: {
 566       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 567                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 568       reg_t sstatus = state.mstatus & mask;
 569       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 570           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 571         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 572       return sstatus;
 573     }
 574     case CSR_SIP: return state.mip & state.mideleg;
 575     case CSR_SIE: return state.mie & state.mideleg;
 576     case CSR_SEPC: return state.sepc;
 577     case CSR_SBADADDR: return state.sbadaddr;
 578     case CSR_STVEC: return state.stvec;
 579     case CSR_SCAUSE:
 580       if (max_xlen > xlen)
 581         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 582       return state.scause;
 583     case CSR_SPTBR:
 584       if (get_field(state.mstatus, MSTATUS_TVM))
 585         require_privilege(PRV_M);
 586       return state.sptbr;
 587     case CSR_SSCRATCH: return state.sscratch;
 588     case CSR_MSTATUS: return state.mstatus;
 589     case CSR_MIP: return state.mip;
 590     case CSR_MIE: return state.mie;
 591     case CSR_MEPC: return state.mepc;
 592     case CSR_MSCRATCH: return state.mscratch;
 593     case CSR_MCAUSE: return state.mcause;
 594     case CSR_MBADADDR: return state.mbadaddr;
 595     case CSR_MISA: return isa;
 596     case CSR_MARCHID: return 0;
 597     case CSR_MIMPID: return 0;
 598     case CSR_MVENDORID: return 0;
 599     case CSR_MHARTID: return id;
 600     case CSR_MTVEC: return state.mtvec;
 601     case CSR_MEDELEG: return state.medeleg;
 602     case CSR_MIDELEG: return state.mideleg;
 603     case CSR_TSELECT: return state.tselect;
 604     case CSR_TDATA1:
 605       if (state.tselect < state.num_triggers) {
 606         reg_t v = 0;
 607         mcontrol_t *mc = &state.mcontrol[state.tselect];
 608         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 609         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 610         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 611         v = set_field(v, MCONTROL_SELECT, mc->select);
 612         v = set_field(v, MCONTROL_TIMING, mc->timing);
 613         v = set_field(v, MCONTROL_ACTION, mc->action);
 614         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 615         v = set_field(v, MCONTROL_MATCH, mc->match);
 616         v = set_field(v, MCONTROL_M, mc->m);
 617         v = set_field(v, MCONTROL_H, mc->h);
 618         v = set_field(v, MCONTROL_S, mc->s);
 619         v = set_field(v, MCONTROL_U, mc->u);
 620         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 621         v = set_field(v, MCONTROL_STORE, mc->store);
 622         v = set_field(v, MCONTROL_LOAD, mc->load);
 623         return v;
 624       } else {
 625         return 0;
 626       }
 627       break;
 628     case CSR_TDATA2:
 629       if (state.tselect < state.num_triggers) {
 630         return state.tdata2[state.tselect];
 631       } else {
 632         return 0;
 633       }
 634       break;
 635     case CSR_TDATA3: return 0;
 636     case CSR_DCSR:
 637       {
 638         uint32_t v = 0;
 639         v = set_field(v, DCSR_XDEBUGVER, 1);
 640         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 641         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 642         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 643         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 644         v = set_field(v, DCSR_STOPCYCLE, 0);
 645         v = set_field(v, DCSR_STOPTIME, 0);
 646         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 647         v = set_field(v, DCSR_STEP, state.dcsr.step);
 648         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 649         return v;
 650       }
 651     case CSR_DPC:
 652       return state.dpc;
 653     case CSR_DSCRATCH:
 654       return state.dscratch;
 655   }
 656   throw trap_illegal_instruction(0);
 657 }
 658
 659 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 660 {
 661   throw trap_illegal_instruction(0);
 662 }
 663
 664 insn_func_t processor_t::decode_insn(insn_t insn)
 665 {
 666   // look up opcode in hash table
 667   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 668   insn_desc_t desc = opcode_cache[idx];
 669
 670   if (unlikely(insn.bits() != desc.match)) {
 671     // fall back to linear search
 672     insn_desc_t* p = &instructions[0];
 673     while ((insn.bits() & p->mask) != p->match)
 674       p++;
 675     desc = *p;
 676
 677     if (p->mask != 0 && p > &instructions[0]) {
 678       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 679         // move to front of opcode list to reduce miss penalty
 680         while (--p >= &instructions[0])
 681           *(p+1) = *p;
 682         instructions[0] = desc;
 683       }
 684     }
 685
 686     opcode_cache[idx] = desc;
 687     opcode_cache[idx].match = insn.bits();
 688   }
 689
 690   return xlen == 64 ? desc.rv64 : desc.rv32;
 691 }
 692
 693 void processor_t::register_insn(insn_desc_t desc)
 694 {
 695   instructions.push_back(desc);
 696 }
 697
 698 void processor_t::build_opcode_map()
 699 {
 700   struct cmp {
 701     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 702       if (lhs.match == rhs.match)
 703         return lhs.mask > rhs.mask;
 704       return lhs.match > rhs.match;
 705     }
 706   };
 707   std::sort(instructions.begin(), instructions.end(), cmp());
 708
 709   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 710     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 711 }
 712
 713 void processor_t::register_extension(extension_t* x)
 714 {
 715   for (auto insn : x->get_instructions())
 716     register_insn(insn);
 717   build_opcode_map();
 718   for (auto disasm_insn : x->get_disasms())
 719     disassembler->add_insn(disasm_insn);
 720   if (ext != NULL)
 721     throw std::logic_error("only one extension may be registered");
 722   ext = x;
 723   x->set_processor(this);
 724 }
 725
 726 void processor_t::register_base_instructions()
 727 {
 728   #define DECLARE_INSN(name, match, mask) \
 729     insn_bits_t name##_match = (match), name##_mask = (mask);
 730   #include "encoding.h"
 731   #undef DECLARE_INSN
 732
 733   #define DEFINE_INSN(name) \
 734     REGISTER_INSN(this, name, name##_match, name##_mask)
 735   #include "insn_list.h"
 736   #undef DEFINE_INSN
 737
 738   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 739   build_opcode_map();
 740 }
 741
 742 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 743 {
 744   switch (addr)
 745   {
 746     case 0:
 747       if (len <= 4) {
 748         memset(bytes, 0, len);
 749         bytes[0] = get_field(state.mip, MIP_MSIP);
 750         return true;
 751       }
 752       break;
 753   }
 754
 755   return false;
 756 }
 757
 758 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 759 {
 760   switch (addr)
 761   {
 762     case 0:
 763       if (len <= 4) {
 764         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 765         return true;
 766       }
 767       break;
 768   }
 769
 770   return false;
 771 }
 772
 773 void processor_t::trigger_updated()
 774 {
 775   mmu->flush_tlb();
 776   mmu->check_triggers_fetch = false;
 777   mmu->check_triggers_load = false;
 778   mmu->check_triggers_store = false;
 779
 780   for (unsigned i = 0; i < state.num_triggers; i++) {
 781     if (state.mcontrol[i].execute) {
 782       mmu->check_triggers_fetch = true;
 783     }
 784     if (state.mcontrol[i].load) {
 785       mmu->check_triggers_load = true;
 786     }
 787     if (state.mcontrol[i].store) {
 788       mmu->check_triggers_store = true;
 789     }
 790   }
 791 }