riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "mmu.h"
   8 #include "icsim.h"
   9
  10 #define MAX_UTS 2048
  11
  12 class sim_t;
  13
  14 class processor_t
  15 {
  16 public:
  17   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
  18   ~processor_t();
  19   void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
  20   void step(size_t n, bool noisy);
  21   void deliver_ipi();
  22
  23 private:
  24   sim_t* sim;
  25
  26   // architected state
  27   reg_t XPR[NXPR];
  28   freg_t FPR[NFPR];
  29
  30   // privileged control registers
  31   reg_t pc;
  32   reg_t epc;
  33   reg_t badvaddr;
  34   reg_t cause;
  35   reg_t evec;
  36   reg_t tohost;
  37   reg_t fromhost;
  38   reg_t pcr_k0;
  39   reg_t pcr_k1;
  40   uint32_t id;
  41   uint32_t sr;
  42   uint32_t count;
  43   uint32_t compare;
  44
  45   bool run;
  46
  47   // unprivileged control registers
  48   uint32_t fsr;
  49
  50   // # of bits in an XPR (32 or 64). (redundant with sr)
  51   int xprlen;
  52
  53   // shared memory
  54   mmu_t mmu;
  55
  56   // counters
  57   reg_t cycle;
  58
  59   // functions
  60   void reset();
  61   void take_interrupt();
  62   void set_sr(uint32_t val);
  63   void set_fsr(uint32_t val);
  64   void take_trap(trap_t t, bool noisy);
  65   void disasm(insn_t insn, reg_t pc);
  66
  67   // vector stuff
  68   void vcfg();
  69   void setvl(int vlapp);
  70
  71   reg_t vecbanks;
  72   uint32_t vecbanks_count;
  73
  74   bool utmode;
  75   int utidx;
  76   int vlmax;
  77   int vl;
  78   int nxfpr_bank;
  79   int nxpr_use;
  80   int nfpr_use;
  81   processor_t* uts[MAX_UTS];
  82
  83   // cache sim
  84   icsim_t* icsim;
  85   icsim_t* dcsim;
  86   icsim_t* itlbsim;
  87   icsim_t* dtlbsim;
  88
  89   friend class sim_t;
  90
  91   #include "dispatch_decl.h"
  92 };
  93
  94 #endif