riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 // architectural state of a RISC-V hart
  35 struct state_t
  36 {
  37   void reset();
  38
  39   reg_t pc;
  40   regfile_t<reg_t, NXPR, true> XPR;
  41   regfile_t<freg_t, NFPR, false> FPR;
  42
  43   // control and status registers
  44   reg_t prv;
  45   reg_t mstatus;
  46   reg_t mepc;
  47   reg_t mbadaddr;
  48   reg_t mscratch;
  49   reg_t mtvec;
  50   reg_t mcause;
  51   reg_t minstret;
  52   reg_t mie;
  53   reg_t mip;
  54   reg_t medeleg;
  55   reg_t mideleg;
  56   reg_t mucounteren;
  57   reg_t mscounteren;
  58   reg_t sepc;
  59   reg_t sbadaddr;
  60   reg_t sscratch;
  61   reg_t stvec;
  62   reg_t sptbr;
  63   reg_t scause;
  64   uint32_t fflags;
  65   uint32_t frm;
  66   bool serialized; // whether timer CSRs are in a well-defined state
  67
  68   reg_t load_reservation;
  69
  70 #ifdef RISCV_ENABLE_COMMITLOG
  71   commit_log_reg_t log_reg_write;
  72   reg_t last_inst_priv;
  73 #endif
  74 };
  75
  76 typedef enum {
  77       HR_NONE,
  78       HR_STEPPED,       // A single step was completed
  79       HR_SWBP,          // sbreak was executed
  80       HR_INTERRUPT,     // Execution interrupted by debugger
  81       HR_CMDLINE,       // Command line requested that the processor start halted
  82       HR_ATTACHED       // Halted because a debugger attached
  83 } halt_reason_t;
  84
  85 // this class represents one processor in a RISC-V machine.
  86 class processor_t : public abstract_device_t
  87 {
  88 public:
  89   processor_t(const char* isa, sim_t* sim, uint32_t id);
  90   ~processor_t();
  91
  92   void set_debug(bool value);
  93   void set_halted(bool value, halt_reason_t reason);
  94   void set_single_step(bool value);
  95   void set_histogram(bool value);
  96   void reset(bool value);
  97   void step(size_t n); // run for n cycles
  98   bool running() { return run; }
  99   void set_csr(int which, reg_t val);
 100   void raise_interrupt(reg_t which);
 101   reg_t get_csr(int which);
 102   mmu_t* get_mmu() { return mmu; }
 103   state_t* get_state() { return &state; }
 104   extension_t* get_extension() { return ext; }
 105   bool supports_extension(unsigned char ext) {
 106     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 107     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 108   }
 109   void set_privilege(reg_t);
 110   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 111   void update_histogram(reg_t pc);
 112
 113   void register_insn(insn_desc_t);
 114   void register_extension(extension_t*);
 115
 116   // MMIO slave interface
 117   bool load(reg_t addr, size_t len, uint8_t* bytes);
 118   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 119
 120 private:
 121   sim_t* sim;
 122   mmu_t* mmu; // main memory is always accessed via the mmu
 123   extension_t* ext;
 124   disassembler_t* disassembler;
 125   state_t state;
 126   uint32_t id;
 127   unsigned max_xlen;
 128   unsigned xlen;
 129   reg_t isa;
 130   std::string isa_string;
 131   bool run; // !reset
 132   // When true, display disassembly of each instruction that's executed.
 133   bool debug;
 134   // TODO: Should this just be rolled into `run`?
 135   bool halted;  // When true, no instructions are executed.
 136   halt_reason_t halt_reason;        // Why is halted true?
 137   // When true, execute exactly one instruction (even if halted is true), then
 138   // set halted to true and single_step to false.
 139   bool single_step;
 140   bool histogram_enabled;
 141
 142   std::vector<insn_desc_t> instructions;
 143   std::map<reg_t,uint64_t> pc_histogram;
 144
 145   static const size_t OPCODE_CACHE_SIZE = 8191;
 146   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 147
 148   void check_timer();
 149   void take_interrupt(); // take a trap if any interrupts are pending
 150   void take_trap(trap_t& t, reg_t epc); // take an exception
 151   void disasm(insn_t insn); // disassemble and print an instruction
 152
 153   friend class sim_t;
 154   friend class mmu_t;
 155   friend class rtc_t;
 156   friend class extension_t;
 157   friend class gdbserver_t;
 158
 159   void parse_isa_string(const char* isa);
 160   void build_opcode_map();
 161   void register_base_instructions();
 162   insn_func_t decode_insn(insn_t insn);
 163 };
 164
 165 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 166
 167 #define REGISTER_INSN(proc, name, match, mask) \
 168   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 169   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 170   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 171
 172 #endif