riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "config.h"
   8
   9 #define MAX_UTS 2048
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15
  16 // this class represents one processor in a RISC-V machine.
  17 class processor_t
  18 {
  19 public:
  20   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  21   ~processor_t();
  22
  23   void step(size_t n, bool noisy); // run for n cycles
  24   void deliver_ipi(); // register an interprocessor interrupt
  25
  26 private:
  27   sim_t& sim;
  28   mmu_t& mmu; // main memory is always accessed via the mmu
  29
  30   // user-visible architected state
  31   regfile_t<reg_t, NXPR, true> XPR;
  32   regfile_t<freg_t, NFPR, false> FPR;
  33   reg_t pc;
  34
  35   // counters
  36   reg_t cycle;
  37
  38   // privileged control registers
  39   reg_t epc;
  40   reg_t badvaddr;
  41   reg_t evec;
  42   reg_t pcr_k0;
  43   reg_t pcr_k1;
  44   reg_t cause;
  45   uint32_t interrupts_pending;
  46   uint32_t id;
  47   uint32_t sr; // only modify the status register using set_pcr()
  48   uint32_t fsr;
  49   uint32_t count;
  50   uint32_t compare;
  51
  52   // # of bits in an XPR (32 or 64). (redundant with sr)
  53   int xprlen;
  54
  55   // is this processor running? (deliver_ipi() sets this)
  56   bool run;
  57
  58   // functions
  59   void reset(); // resets architected state; halts processor if it was running
  60   void take_interrupt(); // take a trap if any interrupts are pending
  61   void set_pcr(int which, reg_t val);
  62   reg_t get_pcr(int which);
  63   void set_fsr(uint32_t val); // set the floating-point status register
  64   void take_trap(reg_t t, bool noisy); // take an exception
  65   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
  66
  67   // vector stuff
  68   void vcfg();
  69   void setvl(int vlapp);
  70
  71   reg_t vecbanks;
  72   uint32_t vecbanks_count;
  73
  74   bool utmode;
  75   uint32_t utidx;
  76   int vlmax;
  77   int vl;
  78   int nxfpr_bank;
  79   int nxpr_use;
  80   int nfpr_use;
  81   processor_t* uts[MAX_UTS];
  82
  83   // this constructor is used for each of the uts
  84   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx);
  85
  86   friend class sim_t;
  87   friend class mmu_t;
  88
  89   #include "dispatch.h"
  90 };
  91
  92 #ifndef RISCV_ENABLE_RVC
  93 # define set_pc(x) \
  94   do { if((x) & (sizeof(insn_t)-1)) \
  95        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
  96        npc = (x); \
  97      } while(0)
  98 #else
  99 # define set_pc(x) \
 100   do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
 101        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 102        npc = (x); \
 103      } while(0)
 104 #endif
 105
 106 #endif