riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "gdbserver.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args)
  29   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
  30     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  31 {
  32   signal(SIGINT, &handle_signal);
  33
  34   for (auto& x : mems)
  35     bus.add_device(x.first, x.second);
  36
  37   bus.add_device(DEBUG_START, &debug_module);
  38
  39   debug_mmu = new mmu_t(this, NULL);
  40
  41   for (size_t i = 0; i < procs.size(); i++) {
  42     procs[i] = new processor_t(isa, this, i, halted);
  43   }
  44
  45   clint.reset(new clint_t(procs));
  46   bus.add_device(CLINT_BASE, clint.get());
  47
  48   make_dtb();
  49 }
  50
  51 sim_t::~sim_t()
  52 {
  53   for (size_t i = 0; i < procs.size(); i++)
  54     delete procs[i];
  55   delete debug_mmu;
  56 }
  57
  58 void sim_thread_main(void* arg)
  59 {
  60   ((sim_t*)arg)->main();
  61 }
  62
  63 void sim_t::main()
  64 {
  65   if (!debug && log)
  66     set_procs_debug(true);
  67
  68   while (!done())
  69   {
  70     if (debug || ctrlc_pressed)
  71       interactive();
  72     else
  73       step(INTERLEAVE);
  74     if (gdbserver) {
  75       gdbserver->handle();
  76     }
  77   }
  78 }
  79
  80 int sim_t::run()
  81 {
  82   host = context_t::current();
  83   target.init(sim_thread_main, this);
  84   return htif_t::run();
  85 }
  86
  87 void sim_t::step(size_t n)
  88 {
  89   for (size_t i = 0, steps = 0; i < n; i += steps)
  90   {
  91     steps = std::min(n - i, INTERLEAVE - current_step);
  92     procs[current_proc]->step(steps);
  93
  94     current_step += steps;
  95     if (current_step == INTERLEAVE)
  96     {
  97       current_step = 0;
  98       procs[current_proc]->yield_load_reservation();
  99       if (++current_proc == procs.size()) {
 100         current_proc = 0;
 101         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 102       }
 103
 104       host->switch_to();
 105     }
 106   }
 107 }
 108
 109 void sim_t::set_debug(bool value)
 110 {
 111   debug = value;
 112 }
 113
 114 void sim_t::set_log(bool value)
 115 {
 116   log = value;
 117 }
 118
 119 void sim_t::set_histogram(bool value)
 120 {
 121   histogram_enabled = value;
 122   for (size_t i = 0; i < procs.size(); i++) {
 123     procs[i]->set_histogram(histogram_enabled);
 124   }
 125 }
 126
 127 void sim_t::set_procs_debug(bool value)
 128 {
 129   for (size_t i=0; i< procs.size(); i++)
 130     procs[i]->set_debug(value);
 131 }
 132
 133 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 134 {
 135   if (addr + len < addr)
 136     return false;
 137   return bus.load(addr, len, bytes);
 138 }
 139
 140 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 141 {
 142   if (addr + len < addr)
 143     return false;
 144   return bus.store(addr, len, bytes);
 145 }
 146
 147 static std::string dts_compile(const std::string& dts)
 148 {
 149   // Convert the DTS to DTB
 150   int dts_pipe[2];
 151   pid_t dts_pid;
 152
 153   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 154     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 155     exit(1);
 156   }
 157
 158   // Child process to output dts
 159   if (dts_pid == 0) {
 160     close(dts_pipe[0]);
 161     int step, len = dts.length();
 162     const char *buf = dts.c_str();
 163     for (int done = 0; done < len; done += step) {
 164       step = write(dts_pipe[1], buf+done, len-done);
 165       if (step == -1) {
 166         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 167         exit(1);
 168       }
 169     }
 170     close(dts_pipe[1]);
 171     exit(0);
 172   }
 173
 174   pid_t dtb_pid;
 175   int dtb_pipe[2];
 176   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 177     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 178     exit(1);
 179   }
 180
 181   // Child process to output dtb
 182   if (dtb_pid == 0) {
 183     dup2(dts_pipe[0], 0);
 184     dup2(dtb_pipe[1], 1);
 185     close(dts_pipe[0]);
 186     close(dts_pipe[1]);
 187     close(dtb_pipe[0]);
 188     close(dtb_pipe[1]);
 189     execl(DTC, DTC, "-O", "dtb", 0);
 190     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 191     exit(1);
 192   }
 193
 194   close(dts_pipe[1]);
 195   close(dts_pipe[0]);
 196   close(dtb_pipe[1]);
 197
 198   // Read-out dtb
 199   std::stringstream dtb;
 200
 201   int got;
 202   char buf[4096];
 203   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 204     dtb.write(buf, got);
 205   }
 206   if (got == -1) {
 207     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 208     exit(1);
 209   }
 210   close(dtb_pipe[0]);
 211
 212   // Reap children
 213   int status;
 214   waitpid(dts_pid, &status, 0);
 215   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 216     std::cerr << "Child dts process failed" << std::endl;
 217     exit(1);
 218   }
 219   waitpid(dtb_pid, &status, 0);
 220   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 221     std::cerr << "Child dtb process failed" << std::endl;
 222     exit(1);
 223   }
 224
 225   return dtb.str();
 226 }
 227
 228 void sim_t::make_dtb()
 229 {
 230   uint32_t reset_vec[] = {
 231     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
 232     0x597,                              // auipc a1, 0
 233     0x58593,                            // addi a1, a1, 0
 234     0xf1402573,                         // csrr a0,mhartid
 235     0x00028067                          // jalr zero, t0, 0 (jump straight to DRAM_BASE)
 236   };
 237   reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
 238
 239   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 240
 241   std::stringstream s;
 242   s << std::dec <<
 243          "/dts-v1/;\n"
 244          "\n"
 245          "/ {\n"
 246          "  #address-cells = <2>;\n"
 247          "  #size-cells = <2>;\n"
 248          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 249          "  model = \"ucbbar,spike-bare\";\n"
 250          "  cpus {\n"
 251          "    #address-cells = <1>;\n"
 252          "    #size-cells = <0>;\n"
 253          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 254   for (size_t i = 0; i < procs.size(); i++) {
 255     s << "    CPU" << i << ": cpu@" << i << " {\n"
 256          "      device_type = \"cpu\";\n"
 257          "      reg = <" << i << ">;\n"
 258          "      status = \"okay\";\n"
 259          "      compatible = \"riscv\";\n"
 260          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 261          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 262          "      clock-frequency = <" << CPU_HZ << ">;\n"
 263          "      CPU" << i << "_intc: interrupt-controller {\n"
 264          "        #interrupt-cells = <1>;\n"
 265          "        interrupt-controller;\n"
 266          "        compatible = \"riscv,cpu-intc\";\n"
 267          "      };\n"
 268          "    };\n";
 269   }
 270   s <<   "  };\n";
 271   for (auto& m : mems) {
 272     s << std::hex <<
 273          "  memory@" << m.first << " {\n"
 274          "    device_type = \"memory\";\n"
 275          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 276                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 277          "  };\n";
 278   }
 279   s <<   "  soc {\n"
 280          "    #address-cells = <2>;\n"
 281          "    #size-cells = <2>;\n"
 282          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 283          "    ranges;\n"
 284          "    clint@" << CLINT_BASE << " {\n"
 285          "      compatible = \"riscv,clint0\";\n"
 286          "      interrupts-extended = <" << std::dec;
 287   for (size_t i = 0; i < procs.size(); i++)
 288     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 289   reg_t clintbs = CLINT_BASE;
 290   reg_t clintsz = CLINT_SIZE;
 291   s << std::hex << ">;\n"
 292          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 293                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 294          "    };\n"
 295          "  };\n"
 296          "};\n";
 297
 298   dts = s.str();
 299   std::string dtb = dts_compile(dts);
 300
 301   rom.insert(rom.end(), dtb.begin(), dtb.end());
 302   const int align = 0x1000;
 303   rom.resize((rom.size() + align - 1) / align * align);
 304
 305   boot_rom.reset(new rom_device_t(rom));
 306   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 307 }
 308
 309 char* sim_t::addr_to_mem(reg_t addr) {
 310   auto desc = bus.find_device(addr);
 311   if (auto mem = dynamic_cast<mem_t*>(desc.device))
 312     return mem->contents() + (addr - desc.base);
 313   return NULL;
 314 }
 315
 316 // htif
 317
 318 void sim_t::idle()
 319 {
 320   target.switch_to();
 321 }
 322
 323 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 324 {
 325   assert(len == 8);
 326   auto data = debug_mmu->load_uint64(taddr);
 327   memcpy(dst, &data, sizeof data);
 328 }
 329
 330 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 331 {
 332   assert(len == 8);
 333   uint64_t data;
 334   memcpy(&data, src, sizeof data);
 335   debug_mmu->store_uint64(taddr, data);
 336 }