riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13
  14 volatile bool ctrlc_pressed = false;
  15 static void handle_signal(int sig)
  16 {
  17   if (ctrlc_pressed)
  18     exit(-1);
  19   ctrlc_pressed = true;
  20   signal(sig, &handle_signal);
  21 }
  22
  23 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
  24              const std::vector<std::string>& args)
  25   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  26     current_step(0), current_proc(0), debug(false)
  27 {
  28   signal(SIGINT, &handle_signal);
  29   // allocate target machine's memory, shrinking it as necessary
  30   // until the allocation succeeds
  31   size_t memsz0 = (size_t)mem_mb << 20;
  32   size_t quantum = 1L << 20;
  33   if (memsz0 == 0)
  34     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  35
  36   memsz = memsz0;
  37   while ((mem = (char*)calloc(1, memsz)) == NULL)
  38     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  39
  40   if (memsz != memsz0)
  41     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  42             (unsigned long)memsz, (unsigned long)memsz0);
  43
  44   debug_mmu = new mmu_t(this, NULL);
  45
  46   for (size_t i = 0; i < procs.size(); i++)
  47     procs[i] = new processor_t(isa, this, i);
  48
  49   rtc.reset(new rtc_t(procs));
  50   make_config_string();
  51 }
  52
  53 sim_t::~sim_t()
  54 {
  55   for (size_t i = 0; i < procs.size(); i++)
  56     delete procs[i];
  57   delete debug_mmu;
  58   free(mem);
  59 }
  60
  61 int sim_t::run()
  62 {
  63   if (!debug && log)
  64     set_procs_debug(true);
  65   while (htif->tick())
  66   {
  67     if (debug || ctrlc_pressed)
  68       interactive();
  69     else
  70       step(INTERLEAVE);
  71   }
  72   return htif->exit_code();
  73 }
  74
  75 void sim_t::step(size_t n)
  76 {
  77   for (size_t i = 0, steps = 0; i < n; i += steps)
  78   {
  79     steps = std::min(n - i, INTERLEAVE - current_step);
  80     procs[current_proc]->step(steps);
  81
  82     current_step += steps;
  83     if (current_step == INTERLEAVE)
  84     {
  85       current_step = 0;
  86       procs[current_proc]->yield_load_reservation();
  87       if (++current_proc == procs.size()) {
  88         current_proc = 0;
  89         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
  90       }
  91
  92       htif->tick();
  93     }
  94   }
  95 }
  96
  97 bool sim_t::running()
  98 {
  99   for (size_t i = 0; i < procs.size(); i++)
 100     if (procs[i]->running())
 101       return true;
 102   return false;
 103 }
 104
 105 void sim_t::stop()
 106 {
 107   procs[0]->state.tohost = 1;
 108   while (htif->tick())
 109     ;
 110 }
 111
 112 void sim_t::set_debug(bool value)
 113 {
 114   debug = value;
 115 }
 116
 117 void sim_t::set_log(bool value)
 118 {
 119   log = value;
 120 }
 121
 122 void sim_t::set_histogram(bool value)
 123 {
 124   histogram_enabled = value;
 125   for (size_t i = 0; i < procs.size(); i++) {
 126     procs[i]->set_histogram(histogram_enabled);
 127   }
 128 }
 129
 130 void sim_t::set_procs_debug(bool value)
 131 {
 132   for (size_t i=0; i< procs.size(); i++)
 133     procs[i]->set_debug(value);
 134 }
 135
 136 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 137 {
 138   if (addr + len < addr)
 139     return false;
 140   return bus.load(addr, len, bytes);
 141 }
 142
 143 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 144 {
 145   if (addr + len < addr)
 146     return false;
 147   return bus.store(addr, len, bytes);
 148 }
 149
 150 void sim_t::make_config_string()
 151 {
 152   reg_t boot_rom_addr = DEFAULT_RSTVEC;
 153   reg_t boot_rom_size = 0x2000;
 154   reg_t rtc_addr = boot_rom_addr + boot_rom_size;
 155   bus.add_device(rtc_addr, rtc.get());
 156
 157   uint32_t reset_vec[8] = {
 158     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 159     0x00028067,                         //   jump straight to DRAM_BASE
 160     0x00000000,                         // reserved
 161     0,                                  // config string pointer
 162     0, 0, 0, 0                          // trap vector
 163   };
 164   reset_vec[3] = boot_rom_addr + sizeof(reset_vec); // config string pointer
 165
 166   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 167
 168   std::stringstream s;
 169   s << std::hex <<
 170         "platform {\n"
 171         "  vendor ucb;\n"
 172         "  arch spike;\n"
 173         "};\n"
 174         "rtc {\n"
 175         "  addr 0x" << rtc_addr << ";\n"
 176         "};\n"
 177         "ram {\n"
 178         "  0 {\n"
 179         "    addr 0x" << DRAM_BASE << ";\n"
 180         "    size 0x" << memsz << ";\n"
 181         "  };\n"
 182         "};\n"
 183         "core {\n";
 184   for (size_t i = 0; i < procs.size(); i++) {
 185     s <<
 186         "  " << i << " {\n"
 187         "    " << "0 {\n" << // hart 0 on core i
 188         "      isa " << procs[i]->isa_string << ";\n"
 189         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 190         "    };\n"
 191         "  };\n";
 192   }
 193   s <<  "};\n";
 194
 195   config_string = s.str();
 196   rom.insert(rom.end(), config_string.begin(), config_string.end());
 197   assert(rom.size() < boot_rom_size);
 198   rom.resize(boot_rom_size);
 199
 200   boot_rom.reset(new rom_device_t(rom));
 201   bus.add_device(boot_rom_addr, boot_rom.get());
 202 }