aabbe79faaf070d5277fa04179615cb2bb1ebba1
1 // See LICENSE for license details.
3 #ifndef _RISCV_SV_DECODE_H
4 #define _RISCV_SV_DECODE_H
14 #define REG_RVC_RS1 0x10
15 #define REG_RVC_RS2 0x20
16 #define REG_RVC_RS1S 0x40
17 #define REG_RVC_RS2S 0x80
20 class sv_insn_t
: public insn_t
23 sv_insn_t(processor_t
*pr
, insn_bits_t bits
, unsigned int f
,
24 uint64_t &p_rd
, uint64_t &p_rs1
, uint64_t &p_rs2
, uint64_t &p_rs3
) :
25 insn_t(bits
), p(pr
), vloop_continue(false), fimap(f
),
26 cached_rd(0xff), cached_rs1(0xff),
27 cached_rs2(0xff), cached_rs3(0xff),
28 offs_rd(0), offs_rs(0),
29 new_offs_rd(0), new_offs_rs(0),
30 prd(p_rd
), prs1(p_rs1
), prs2(p_rs2
), prs3(p_rs3
) {}
31 uint64_t rd () { return predicated(_rd (), offs_rd
, prd
); }
32 uint64_t rs1() { return predicated(_rs1(), offs_rs
, prs1
); }
33 uint64_t rs2() { return predicated(_rs2(), offs_rs
, prs2
); }
34 uint64_t rs3() { return predicated(_rs3(), offs_rs
, prs3
); }
35 uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs
, prs1
); }
36 uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs
, prs1
); }
37 uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs
, prs2
); }
38 uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs
, prs2
); }
40 uint64_t _rd () { return _remap(insn_t::rd (), fimap
& REG_RD
,
41 offs_rd
, cached_rd
, new_offs_rd
); }
42 uint64_t _rs1() { return _remap(insn_t::rs1(), fimap
& REG_RS1
,
43 offs_rs
, cached_rs1
, new_offs_rs
); }
44 uint64_t _rs2() { return _remap(insn_t::rs2(), fimap
& REG_RS2
,
45 offs_rs
, cached_rs2
, new_offs_rs
); }
46 uint64_t _rs3() { return _remap(insn_t::rs3(), fimap
& REG_RS3
,
47 offs_rs
, cached_rs3
, new_offs_rs
); }
48 uint64_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(), fimap
& REG_RVC_RS1
,
49 offs_rs
, cached_rs1
, new_offs_rs
); }
50 uint64_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(), fimap
& REG_RVC_RS1S
,
51 offs_rs
, cached_rs1
, new_offs_rs
); }
52 uint64_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(), fimap
& REG_RVC_RS2
,
53 offs_rs
, cached_rs2
, new_offs_rs
); }
54 uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap
& REG_RVC_RS2S
,
55 offs_rs
, cached_rs2
, new_offs_rs
); }
57 void reset_caches(void)
63 offs_rd
= new_offs_rd
;
64 offs_rs
= new_offs_rs
;
67 bool sv_check_reg(bool intreg
, uint64_t reg
);
68 sv_reg_entry
* get_regentry(uint64_t reg
, bool isint
);
69 sv_pred_entry
* get_predentry(uint64_t reg
, bool isint
);
70 reg_t
predicate(uint64_t reg
, bool isint
, bool &zeroing
);
72 void reset_vloop_check(void) { vloop_continue
= false; }
73 bool stop_vloop(void);
75 int rd_offs(void) { return offs_rd
; }
76 int rs_offs(void) { return offs_rs
; }
77 int rd_offs_inc(void) { offs_rd
+= 1; return offs_rd
; }
78 int rs_offs_inc(void) { offs_rs
+= 1; return offs_rs
; }
97 // remaps the register through the lookup table.
98 // will need to take the current loop index/offset somehow
99 uint64_t remap(uint64_t reg
, bool isint
, int &offs
, int &newoffs
);
101 // cached version of remap: if remap is called multiple times
102 // by an emulated instruction it would increment the loop offset
103 // before it's supposed to.
104 uint64_t _remap(uint64_t reg
, bool isint
, int &offs
,
105 uint64_t &cached
, int &newoffs
)
109 cached
= remap(reg
, isint
, offs
, newoffs
);
113 if (sv_check_reg(isint
, reg
))
115 vloop_continue
= true;
121 uint64_t predicated(uint64_t reg
, int offs
, uint64_t pred
);