rvc/rvc.h

   1 #ifndef _RVC_H
   2 #define _RVC_H
   3
   4 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
   5 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
   6 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
   7
   8 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
   9 #define CRD XPR.write_port(CRD_REGNUM)
  10 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
  11 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
  12 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
  13 #define CIMM5U ((insn.bits >> 5) & 0x1f)
  14 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
  15 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
  16 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
  17 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
  18
  19 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
  20 #define rvc_rd_regmap rvc_rs1_regmap
  21 #define rvc_rs2b_regmap rvc_rs1_regmap
  22 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
  23 #define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
  24 #define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
  25 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
  26 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
  27 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
  28 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
  29
  30 #endif