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[libreriscv.git] / shakti / m_class / AXI.mdwn
1 # AXI Bridge
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3 See also [[wishbone]] Bus
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5 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
6 * <https://github.com/alexforencich/verilog-axis>
7 * <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
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9 # AXI4 in migen
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11 Implementations of AXI4 in nmigen (not just bridges)
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13 * <https://github.com/peteut/migen-axi>
14 * <https://github.com/apertus-open-source-cinema/nmigen-gateware>
15 * nmigen-soc planning to have AXI4