shakti/m_class/I2S.mdwn

   1 # I2S
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=3>
   4 * <https://github.com/skristiansson/i2s>
   5 * <https://en.wikipedia.org/wiki/I%C2%B2S>
   6 * <http://www.ti.com/lit/an/snla221/snla221.pdf>
   7 * <https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf>
   8
   9 Question: how does I2S do 4-wire output?
  10
  11 Question: how does I2S fit in with [[AC97]]?
  12
  13 # Breakout Boards
  14
  15 * <https://www.sparkfun.com/products/12767>
  16 * <https://cdn.sparkfun.com/datasheets/Dev/Teensy/SGTL5000.pdf>
  17
  18 Audio Master Controller
  19 =======================
  20
  21 Terminology and lots of confusion. I2S, AC97, PCM, TDM ???  :-)
  22
  23
  24 # Physical interface
  25
  26 Both "I2S" and "AC97" use the same physical interface, which is
  27 really what "I2S" stands for. AC97 defined a TDM mechanism for
  28 fancy data packing.
  29
  30 Multi bit or single bit ?
  31
  32 So far I have not seen a single device with multiple serial data
  33 lines (but same bit and word clock). My understanding that multi
  34 bit will allow for multiple codecs, but since there is no particular
  35 standard for that, I would not recommend implementing this.
  36
  37 A single I2S interface in TDM/AC97 mode, can support over 32
  38 channels of audio. It will be of advantage to have multiple I2S
  39 interfaces (complete blocks), as it will give most flexibility.
  40 I think two I2S interfaces should be sufficient (one internal
  41 link to Bluetooth and such, and one to a codec for external audio,
  42 like speaker, headphones, microphones).
  43
  44 So I propose to have each I2S link look like this:
  45 * bit clock, input (may be optionally also an output - TBD)
  46 * word/frame/lr/sync clock, output
  47 * serial data, input
  48 * serial data, output
  49 * coder reset, output, optional
  50
  51 # Protocols
  52
  53 I don't think there is an easy way out, we need to support all
  54 protocols there are.
  55
  56 * basic I2S L/R
  57 * PCM (very similar to I2S L/R)
  58 * AC97/TDM
  59
  60 # Data Alignment
  61
  62 Powerful data alignment is very important. It is relatively easy to
  63 implement in hardware, and is reduces the load on the CPU when moving
  64 audio data between different interfaces.
  65 * 8, 16, 18, 20, 24, 32 bit sample sizes supported
  66 * Left/Right alignment
  67 * Packed/unpacked streams
  68
  69 # SoC Interface
  70
  71 Two interfaces will be implemented:
  72
  73 * AXI Light for Register file access
  74 * AXI Streaming Interface for data
  75
  76 Both interfaces will be slave interfaces. An external DMA can
  77 be added to move data from AXI MM to AXI Streaming interface.