shakti/m_class/IOcell.mdwn

   1 # IOcell
   2
   3 [[iopad.jpg]]
   4
   5 here is a list of requirements:
   6
   7 * pull-up control which switches in a 10k (50k?) resistor
   8
   9 * pull-down control which switches in a 10k (50k?) resistor
  10
  11 * a "mode" setting that flips it between Open-Drain (floating if
  12   LO, and pulled to GND if HI) and CMOS (MOSFET) Push-Push modes.
  13   see https://en.wikipedia.org/wiki/Open_collector#MOSFET for details on
  14   Open Drain (requires a MOSFET).
  15
  16 * a "hysteresis" setting that controls the input schottky filter's
  17   sensitivity.  this is important for push-buttons for example,
  18   to stop spiking (bounce) that would be amplified and result in
  19   massive noise spikes onto all wires throughout that entire area
  20   of the chip.  low middle and high settings are needed to cover
  21   filtering ranges of say 2mhz, 5mhz, 10mhz and unlimited (disabling
  22   hysteresis).  looking at STM32F documentation helps here as does this
  23   https://electronics.stackexchange.com/questions/156930/stm32-understanding-gpio-settings
  24
  25 * an input-enable selector
  26
  27 * an output-enable selector
  28
  29 * also required is a means to change the current output: 10mA, 20mA,
  30 30mA and 40mA are reasonable
  31
  32 * also the input and output really need *automatic* level-shifting,
  33   built-in to the IO cell.  so whilst there is a VDD for driving the pad
  34   (and setting the CMOS threshold levels for input), there is *also* a need
  35   for an IO VREF.  this is *important*.  the input and output needs to be
  36   CMOS push-push (standard logic) whilst the IO pad needs to be switchable
  37   between OD and PP.
  38
  39 * input threshold voltages that trigger the input from HI to LO should
  40   be standard CMOS voltage levels (even in OD mode), which i believe is
  41   below 0.3 * VDD for "LO" and 0.7 * VDD for "HI"
  42
  43 * output voltage levels should be as close to 0 as possible for LO (0.3v
  44   or below @ nominal temperature) and as close to VDD as possible for HI
  45   (VDD-0.3v or above @ nominal temperature).
  46
  47 * some ability to protect itself from over-driving (current fights)
  48   when in output mode are a must.
  49
  50 * the ability to protect itself from *being* over-driven when in input
  51   mode is not strictly necessary (over-voltage tolerance e.g. 5V tolerance
  52   when VDD is well below that) but would be nice to have as an option
  53   (two variants: one for ECs which need 5V tolerance and one for SoCs
  54   where it's not).
  55
  56