projects / libreriscv.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
add more interfaces
[libreriscv.git] / shakti / m_class / RGMII.mdwn
1 # RGMII Gigabit Ethernet PHY
2
3 *
4 * <https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/eth_mac_1g_rgmii.v>
http://libre-riscv.org ikiwiki