(no commit message)
[libreriscv.git] / shakti / m_class / SPI.mdwn
1 # SPI
2
3 see also [[QSPI]]
4
5 * <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
6 * Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
7 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
8 includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM. Also included
9 is a Watchdog Timer and others.
10 * APB to SPI <https://opencores.org/project,apb2spi>
11 * ASIC-proven <https://opencores.org/project,spi_master_slave>
12 * Wishbone-compliant <https://opencores.org/project,simple_spi>
13 * Raptor Engineering litespi, improved <
14 https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litespi>
15 * Also Shakti E-Class peripheral set in BSV