shakti/m_class/pinmux.mdwn

   1 # Pin Multiplexing
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=8>
   4 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   5   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   6   is a Watchdog Timer and others.
   7 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   8   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
   9
  10 Surprisingly complex!
  11
  12 # Requirements
  13
  14 "to create a general-purpose libre-licensed pinmux
  15 module that can be used with a wide range of interfaces that have
  16 Open-Drain, Push-Push *and bi-directional* capabilities, as well as
  17 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
  18 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
  19 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
  20
  21 * Number of wires shall be minimised especially in cases where
  22   outputs need to change characteristics of the IO pad (puen, oe)
  23 * There shall be no short-circuits created by multiple input
  24   pins trying to drive the same input function
  25 * The IO pad shall have pull-up enable, pull-down enable, variable
  26   frequency de-bounce, tri-state capability, Open Drain and CMOS
  27   Push-Push.
  28 * The amount of latency (gates in between I/O pad and function)
  29   shall be minimised
  30
  31 ## Analysis
  32
  33 Questions:
  34
  35 * Can damage occur (to the ASIC) by outputs being short-circuited to outputs
  36   in any way?
  37   A partial analysis showed that because outputs are one-to-many, there should
  38   not be a possibility for that to occur.  However what if a function is
  39   bi-directional?
  40 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
  41   to be only done on EINT?
  42 * Can the input mux be turned round and "selector" logic added so that
  43   there is no possibility of damage to inputs?
  44
  45 # Images
  46
  47 * [[mygpiomux.jpg]]
  48
  49 # GSoC2018
  50
  51 Introductions:
  52
  53 * Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
  54   advocate, assembly-level programming and disassembly, python, c, c++,
  55   gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
  56   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
  57   and currently responsible for coordinating the design of a fully Libre
  58   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
  59   not much experience at verilog (have done a couple of tutorials).
  60 * Xing GUO(xing) - undergraduate (3rd year) from Southeast
  61   University, EE student, C/C++, Python, Verilog, assembly (not very proficient),
  62   Haskell (not very proficient). RTL design, server maintenance.
  63   E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
  64 * Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
  65   at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
  66   Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
  67
  68 Hardware available:
  69
  70 * lkcl: ZC706
  71 * xing: zynq-7020 and Xilinx XC7A100T-484
  72
  73 # Discussion and Links
  74
  75 * <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
  76 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
  77 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
  78
  79 ## Some Useful Resource
  80
  81 * <https://docs.scala-lang.org/tour/tour-of-scala.html> A brief Scala tutorial
  82 * <https://github.com/ucb-bar/chisel-tutorial> A brief Chisel tutorial
  83
  84 # Pinouts Specification
  85
  86 Covered in [[pinouts]].  The general idea is to target several
  87 distinct applications and, by trial-and-error, create a pinmux table that
  88 successfully covers all the target scenarios by providing absolutely all
  89 required functions for each and every target.  A few general rules:
  90
  91 * Different functions (SPI, I2C) which overlap on the same pins on one
  92  bank should also be duplicated on completely different banks, both from
  93  each other and also the bank on which they overlap.  With each bank having
  94  separate Power Domains this strategy increases the chances of being able
  95  to place low-power and high-power peripherals and sensors on separate
  96  GPIO banks without needing external level-shifters.
  97 * Functions which have optional bus-widths (eMMC: 1/2/4/8) may have more
  98  functions overlapping them than would otherwise normally be considered.
  99 * Then the same overlapped high-order bus pins can also be mapped onto
 100  other pins.  This particularly applies to the very large buses, such
 101  as FlexBus (over 50 pins).  However if the overlapped pins are on a
 102  different bank it becomes necessary to have both banks run in the same
 103  GPIO Power Domain.
 104 * All functions should really be pin-muxed at least twice, preferably
 105  three times.  Four or more times on average makes it pointless to
 106  even have four-way pinmuxing at all, so this should be avoided.
 107  The only exceptions (functions which have not been pinmuxed multiple
 108  times) are the RGB/TTL LCD channel, and both ULPI interfaces.
 109
 110 # GPIO Pinmux Power Domains
 111
 112 Of particular importance is the Power Domains for the GPIO.  Realistically
 113 it has to be flexible (simplest option: recommended to be between
 114 1.8v and 3.3v) as the majority of low-cost mass-produced sensors and
 115 peripherals on I2C, SPI, UART and SD/MMC are at or are compatible with
 116 this voltage range.  Long-tail (older / stable / low-cost / mass-produced)
 117 peripherals in particular tend to be 3.3v, whereas newer ones with a
 118 particular focus on Mobile tend to be 1.2v to 1.8v.
 119
 120 A large percentage of sensors and peripherals have separate IO voltage
 121 domains from their main supply voltage: a good example is the SN75LVDS83b
 122 which has one power domain for the RGB/TTL I/O, one for the LVDS output,
 123 and one for the internal logic controller (typical deployments tend not
 124 to notice the different power-domain capability, as they usually supply all
 125 three voltages at 3.3v).
 126
 127 Relying on this capability, however, by selecting a fixed voltage for
 128 the entire SoC's GPIO domain, is simply not a good idea: all sensors
 129 and peripherals which do not have a variable (VREF) capability for the
 130 logic side, or coincidentally are not at the exact same fixed voltage,
 131 will simply not be compatible if they are high-speed CMOS-level push-push
 132 driven.  Open-Drain on the other hand can be handled with a MOSFET for
 133 two-way or even a diode for one-way depending on the levels, but this means
 134 significant numbers of external components if the number of lines is large.
 135
 136 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 137 problem: external level-shifting is required on pretty much absolutely every
 138 single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
 139 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 140 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 141 worth of level-shifting, which is not just costly
 142 but also a huge amount of PCB space: bear in mind that for level-shifting, an
 143 IC with **double** the number of pins being level-shifted is required.
 144
 145 Given that level-shifting is an unavoidable necessity, and external
 146 level-shifting has such high cost(s), the workable solution is to
 147 actually include GPIO-group level-shifting actually on the SoC die,
 148 after the pin-muxer at the front-end (on the I/O pads of the die),
 149 on a per-bank basis.  This is an extremely common technique that is
 150 deployed across a very wide range of mass-volume SoCs.
 151
 152 One very useful side-effect for example of a variable Power Domain voltage
 153 on a GPIO bank containing SD/MMC functionality is to be able to change the
 154 bank's voltage from 3.3v to 1.8v, to match an SD Card's capabilities, as
 155 permitted under the SD/MMC Specification.  The alternative is to be forced to
 156 deploy an external level-shifter IC (if PCB space and BOM target allows) or to
 157 fix the voltage at 3.3v and thus lose access to the low-power and higher-speed
 158 capabilities of modern SD Cards.
 159
 160 In summary: putting level shifters right at the I/O pads of the SoC, after
 161 the pin-mux (so that the core logic remains at the core voltage) is a
 162 cost-effective solution that can have additional unintended side-benefits
 163 and cost savings beyond simply saving on external level-shifting components
 164 and board space.
 165