shakti/m_class/pinmux.mdwn

   1 # Pin Multiplexing
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=8>
   4 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   5   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   6   is a Watchdog Timer and others.
   7 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   8   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
   9
  10 Complex!
  11
  12 # Requirements
  13
  14 "to create a general-purpose libre-licensed pinmux
  15 module that can be used with a wide range of interfaces that have
  16 Open-Drain, Push-Push *and bi-directional* capabilities, as well as
  17 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
  18 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
  19 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
  20
  21 ## Analysis
  22
  23 Questions:
  24
  25 * Can damage occur by outputs being short-circuited to outputs in any way?
  26   A partial analysis showed that because outputs are one-to-many, there should
  27   not be a possibility for that to occur.  However what if a function is
  28   bi-directional?
  29 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
  30   to be only done on EINT?
  31
  32 # GSoC2018
  33
  34 Introductions:
  35
  36 * Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
  37   advocate, assembly-level programming and disassembly, python, c, c++,
  38   gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
  39   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
  40   and currently responsible for coordinating the design of a fully Libre
  41   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
  42
  43 # Discussion and Links
  44
  45 * <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
  46 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
  47 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
  48
  49 # Pinouts Specification
  50
  51 Covered in [[pinouts]].  The general idea is to target several
  52 distinct applications and, by trial-and-error, create a pinmux table that
  53 successfully covers all the target scenarios by providing absolutely all
  54 required functions for each and every target.  A few general rules:
  55
  56 * Different functions (SPI, I2C) which overlap on the same pins on one
  57  bank should also be duplicated on completely different banks, both from
  58  each other and also the bank on which they overlap.  With each bank having
  59  separate Power Domains this strategy increases the chances of being able
  60  to place low-power and high-power peripherals and sensors on separate
  61  GPIO banks without needing external level-shifters.
  62 * Functions which have optional bus-widths (eMMC: 1/2/4/8) may have more
  63  functions overlapping them than would otherwise normally be considered.
  64 * Then the same overlapped high-order bus pins can also be mapped onto
  65  other pins.  This particularly applies to the very large buses, such
  66  as FlexBus (over 50 pins).  However if the overlapped pins are on a
  67  different bank it becomes necessary to have both banks run in the same
  68  GPIO Power Domain.
  69 * All functions should really be pin-muxed at least twice, preferably
  70  three times.  Four or more times on average makes it pointless to
  71  even have four-way pinmuxing at all, so this should be avoided.
  72  The only exceptions (functions which have not been pinmuxed multiple
  73  times) are the RGB/TTL LCD channel, and both ULPI interfaces.
  74
  75 # GPIO Pinmux Power Domains
  76
  77 Of particular importance is the Power Domains for the GPIO.  Realistically
  78 it has to be flexible (simplest option: recommended to be between
  79 1.8v and 3.3v) as the majority of low-cost mass-produced sensors and
  80 peripherals on I2C, SPI, UART and SD/MMC are at or are compatible with
  81 this voltage range.  Long-tail (older / stable / low-cost / mass-produced)
  82 peripherals in particular tend to be 3.3v, whereas newer ones with a
  83 particular focus on Mobile tend to be 1.2v to 1.8v.
  84
  85 A large percentage of sensors and peripherals have separate IO voltage
  86 domains from their main supply voltage: a good example is the SN75LVDS83b
  87 which has one power domain for the RGB/TTL I/O, one for the LVDS output,
  88 and one for the internal logic controller (typical deployments tend not
  89 to notice the different power-domain capability, as they usually supply all
  90 three voltages at 3.3v).
  91
  92 Relying on this capability, however, by selecting a fixed voltage for
  93 the entire SoC's GPIO domain, is simply not a good idea: all sensors
  94 and peripherals which do not have a variable (VREF) capability for the
  95 logic side, or coincidentally are not at the exact same fixed voltage,
  96 will simply not be compatible if they are high-speed CMOS-level push-push
  97 driven.  Open-Drain on the other hand can be handled with a MOSFET for
  98 two-way or even a diode for one-way depending on the levels, but this means
  99 significant numbers of external components if the number of lines is large.
 100
 101 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 102 problem: external level-shifting is required on pretty much absolutely every
 103 single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
 104 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 105 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 106 worth of level-shifting, which is not just costly
 107 but also a huge amount of PCB space: bear in mind that for level-shifting, an
 108 IC with **double** the number of pins being level-shifted is required.
 109
 110 Given that level-shifting is an unavoidable necessity, and external
 111 level-shifting has such high cost(s), the workable solution is to
 112 actually include GPIO-group level-shifting actually on the SoC die,
 113 after the pin-muxer at the front-end (on the I/O pads of the die),
 114 on a per-bank basis.  This is an extremely common technique that is
 115 deployed across a very wide range of mass-volume SoCs.
 116
 117 One very useful side-effect for example of a variable Power Domain voltage
 118 on a GPIO bank containing SD/MMC functionality is to be able to change the
 119 bank's voltage from 3.3v to 1.8v, to match an SD Card's capabilities, as
 120 permitted under the SD/MMC Specification.  The alternative is to be forced to
 121 deploy an external level-shifter IC (if PCB space and BOM target allows) or to
 122 fix the voltage at 3.3v and thus lose access to the low-power and higher-speed
 123 capabilities of modern SD Cards.
 124
 125 In summary: putting level shifters right at the I/O pads of the SoC, after
 126 the pin-mux (so that the core logic remains at the core voltage) is a
 127 cost-effective solution that can have additional unintended side-benefits
 128 and cost savings beyond simply saving on external level-shifting components
 129 and board space.
 130