shakti/m_class/pinmux.mdwn

   1 # Pin Multiplexing
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=8>
   4 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   5   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   6   is a Watchdog Timer and others.
   7 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   8   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
   9
  10 Surprisingly complex!
  11
  12 # Requirements
  13
  14 "to create a general-purpose libre-licensed pinmux
  15 module that can be used with a wide range of interfaces that have
  16 Open-Drain, Push-Push *and bi-directional* capabilities, as well as
  17 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
  18 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
  19 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
  20
  21 * Number of wires shall be minimised especially in cases where
  22   the IO pad (puen, oe) need to change under the control of the
  23   function (not the GPIO registers).
  24 * There shall be no short-circuits created by multiple input
  25   pins trying to drive the same input function
  26 * The IO pad shall have pull-up enable, pull-down enable, variable
  27   frequency de-bounce, tri-state capability, Open Drain and CMOS
  28   Push-Push.
  29 * The amount of latency (gates in between I/O pad and function)
  30   shall be minimised
  31
  32 ## Analysis
  33
  34 Questions:
  35
  36 * Can damage occur (to the ASIC) by outputs being short-circuited to outputs
  37   in any way?
  38   A partial analysis showed that because outputs are one-to-many, there should
  39   not be a possibility for that to occur.  However what if a function is
  40   bi-directional?
  41 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
  42   to be only done on EINT?
  43 * Can the input mux be turned round and "selector" logic added so that
  44   there is no possibility of damage to inputs?
  45
  46 # Images
  47
  48 * [[mygpiomux.jpg]]
  49
  50 # GSoC2018
  51
  52 Introductions:
  53
  54 * Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
  55   advocate, assembly-level programming and disassembly, python, c, c++,
  56   gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
  57   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
  58   and currently responsible for coordinating the design of a fully Libre
  59   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
  60   not much experience at verilog (have done a couple of tutorials).
  61 * Xing GUO(xing) - undergraduate (3rd year) from Southeast
  62   University, EE student, C/C++, Python, Verilog, assembly (not very proficient),
  63   Haskell (not very proficient). RTL design, server maintenance.
  64   E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
  65 * Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
  66   at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
  67   Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
  68
  69 Hardware available:
  70
  71 * lkcl: ZC706
  72 * xing: zynq-7020 and Xilinx XC7A100T-484
  73
  74 # Discussion and Links
  75
  76 * <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
  77 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
  78 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
  79
  80 ## Some Useful Resource
  81
  82 * <https://docs.scala-lang.org/tour/tour-of-scala.html> A brief Scala tutorial
  83 * <https://github.com/ucb-bar/chisel-tutorial> A brief Chisel tutorial
  84
  85 # Pinouts Specification
  86
  87 Covered in [[pinouts]].  The general idea is to target several
  88 distinct applications and, by trial-and-error, create a pinmux table that
  89 successfully covers all the target scenarios by providing absolutely all
  90 required functions for each and every target.  A few general rules:
  91
  92 * Different functions (SPI, I2C) which overlap on the same pins on one
  93  bank should also be duplicated on completely different banks, both from
  94  each other and also the bank on which they overlap.  With each bank having
  95  separate Power Domains this strategy increases the chances of being able
  96  to place low-power and high-power peripherals and sensors on separate
  97  GPIO banks without needing external level-shifters.
  98 * Functions which have optional bus-widths (eMMC: 1/2/4/8) may have more
  99  functions overlapping them than would otherwise normally be considered.
 100 * Then the same overlapped high-order bus pins can also be mapped onto
 101  other pins.  This particularly applies to the very large buses, such
 102  as FlexBus (over 50 pins).  However if the overlapped pins are on a
 103  different bank it becomes necessary to have both banks run in the same
 104  GPIO Power Domain.
 105 * All functions should really be pin-muxed at least twice, preferably
 106  three times.  Four or more times on average makes it pointless to
 107  even have four-way pinmuxing at all, so this should be avoided.
 108  The only exceptions (functions which have not been pinmuxed multiple
 109  times) are the RGB/TTL LCD channel, and both ULPI interfaces.
 110
 111 # GPIO Pinmux Power Domains
 112
 113 Of particular importance is the Power Domains for the GPIO.  Realistically
 114 it has to be flexible (simplest option: recommended to be between
 115 1.8v and 3.3v) as the majority of low-cost mass-produced sensors and
 116 peripherals on I2C, SPI, UART and SD/MMC are at or are compatible with
 117 this voltage range.  Long-tail (older / stable / low-cost / mass-produced)
 118 peripherals in particular tend to be 3.3v, whereas newer ones with a
 119 particular focus on Mobile tend to be 1.2v to 1.8v.
 120
 121 A large percentage of sensors and peripherals have separate IO voltage
 122 domains from their main supply voltage: a good example is the SN75LVDS83b
 123 which has one power domain for the RGB/TTL I/O, one for the LVDS output,
 124 and one for the internal logic controller (typical deployments tend not
 125 to notice the different power-domain capability, as they usually supply all
 126 three voltages at 3.3v).
 127
 128 Relying on this capability, however, by selecting a fixed voltage for
 129 the entire SoC's GPIO domain, is simply not a good idea: all sensors
 130 and peripherals which do not have a variable (VREF) capability for the
 131 logic side, or coincidentally are not at the exact same fixed voltage,
 132 will simply not be compatible if they are high-speed CMOS-level push-push
 133 driven.  Open-Drain on the other hand can be handled with a MOSFET for
 134 two-way or even a diode for one-way depending on the levels, but this means
 135 significant numbers of external components if the number of lines is large.
 136
 137 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 138 problem: external level-shifting is required on pretty much absolutely every
 139 single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
 140 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 141 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 142 worth of level-shifting, which is not just costly
 143 but also a huge amount of PCB space: bear in mind that for level-shifting, an
 144 IC with **double** the number of pins being level-shifted is required.
 145
 146 Given that level-shifting is an unavoidable necessity, and external
 147 level-shifting has such high cost(s), the workable solution is to
 148 actually include GPIO-group level-shifting actually on the SoC die,
 149 after the pin-muxer at the front-end (on the I/O pads of the die),
 150 on a per-bank basis.  This is an extremely common technique that is
 151 deployed across a very wide range of mass-volume SoCs.
 152
 153 One very useful side-effect for example of a variable Power Domain voltage
 154 on a GPIO bank containing SD/MMC functionality is to be able to change the
 155 bank's voltage from 3.3v to 1.8v, to match an SD Card's capabilities, as
 156 permitted under the SD/MMC Specification.  The alternative is to be forced to
 157 deploy an external level-shifter IC (if PCB space and BOM target allows) or to
 158 fix the voltage at 3.3v and thus lose access to the low-power and higher-speed
 159 capabilities of modern SD Cards.
 160
 161 In summary: putting level shifters right at the I/O pads of the SoC, after
 162 the pin-mux (so that the core logic remains at the core voltage) is a
 163 cost-effective solution that can have additional unintended side-benefits
 164 and cost savings beyond simply saving on external level-shifting components
 165 and board space.
 166