shakti/m_class/pinmux.mdwn

   1 # Pin Multiplexing
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=8>
   4 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   5   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   6   is a Watchdog Timer and others.
   7 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   8   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
   9
  10 Complex!
  11
  12 # Requirements
  13
  14 "to create a general-purpose libre-licensed pinmux
  15 module that can be used with a wide range of interfaces that have
  16 Open-Drain, Push-Push *and bi-directional* capabilities, as well as
  17 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
  18 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
  19 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
  20
  21 ## Analysis
  22
  23 Questions:
  24
  25 * Can damage occur (to the ASIC) by outputs being short-circuited to outputs
  26   in any way?
  27   A partial analysis showed that because outputs are one-to-many, there should
  28   not be a possibility for that to occur.  However what if a function is
  29   bi-directional?
  30 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
  31   to be only done on EINT?
  32
  33 # GSoC2018
  34
  35 Introductions:
  36
  37 * Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
  38   advocate, assembly-level programming and disassembly, python, c, c++,
  39   gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
  40   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
  41   and currently responsible for coordinating the design of a fully Libre
  42   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
  43
  44 Hardware available:
  45
  46 * lkcl: ZC706
  47 * xing: zynq-7020 and Xilinx XC7A100T-484
  48
  49 # Discussion and Links
  50
  51 * <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
  52 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
  53 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
  54
  55 # Pinouts Specification
  56
  57 Covered in [[pinouts]].  The general idea is to target several
  58 distinct applications and, by trial-and-error, create a pinmux table that
  59 successfully covers all the target scenarios by providing absolutely all
  60 required functions for each and every target.  A few general rules:
  61
  62 * Different functions (SPI, I2C) which overlap on the same pins on one
  63  bank should also be duplicated on completely different banks, both from
  64  each other and also the bank on which they overlap.  With each bank having
  65  separate Power Domains this strategy increases the chances of being able
  66  to place low-power and high-power peripherals and sensors on separate
  67  GPIO banks without needing external level-shifters.
  68 * Functions which have optional bus-widths (eMMC: 1/2/4/8) may have more
  69  functions overlapping them than would otherwise normally be considered.
  70 * Then the same overlapped high-order bus pins can also be mapped onto
  71  other pins.  This particularly applies to the very large buses, such
  72  as FlexBus (over 50 pins).  However if the overlapped pins are on a
  73  different bank it becomes necessary to have both banks run in the same
  74  GPIO Power Domain.
  75 * All functions should really be pin-muxed at least twice, preferably
  76  three times.  Four or more times on average makes it pointless to
  77  even have four-way pinmuxing at all, so this should be avoided.
  78  The only exceptions (functions which have not been pinmuxed multiple
  79  times) are the RGB/TTL LCD channel, and both ULPI interfaces.
  80
  81 # GPIO Pinmux Power Domains
  82
  83 Of particular importance is the Power Domains for the GPIO.  Realistically
  84 it has to be flexible (simplest option: recommended to be between
  85 1.8v and 3.3v) as the majority of low-cost mass-produced sensors and
  86 peripherals on I2C, SPI, UART and SD/MMC are at or are compatible with
  87 this voltage range.  Long-tail (older / stable / low-cost / mass-produced)
  88 peripherals in particular tend to be 3.3v, whereas newer ones with a
  89 particular focus on Mobile tend to be 1.2v to 1.8v.
  90
  91 A large percentage of sensors and peripherals have separate IO voltage
  92 domains from their main supply voltage: a good example is the SN75LVDS83b
  93 which has one power domain for the RGB/TTL I/O, one for the LVDS output,
  94 and one for the internal logic controller (typical deployments tend not
  95 to notice the different power-domain capability, as they usually supply all
  96 three voltages at 3.3v).
  97
  98 Relying on this capability, however, by selecting a fixed voltage for
  99 the entire SoC's GPIO domain, is simply not a good idea: all sensors
 100 and peripherals which do not have a variable (VREF) capability for the
 101 logic side, or coincidentally are not at the exact same fixed voltage,
 102 will simply not be compatible if they are high-speed CMOS-level push-push
 103 driven.  Open-Drain on the other hand can be handled with a MOSFET for
 104 two-way or even a diode for one-way depending on the levels, but this means
 105 significant numbers of external components if the number of lines is large.
 106
 107 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 108 problem: external level-shifting is required on pretty much absolutely every
 109 single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
 110 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 111 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 112 worth of level-shifting, which is not just costly
 113 but also a huge amount of PCB space: bear in mind that for level-shifting, an
 114 IC with **double** the number of pins being level-shifted is required.
 115
 116 Given that level-shifting is an unavoidable necessity, and external
 117 level-shifting has such high cost(s), the workable solution is to
 118 actually include GPIO-group level-shifting actually on the SoC die,
 119 after the pin-muxer at the front-end (on the I/O pads of the die),
 120 on a per-bank basis.  This is an extremely common technique that is
 121 deployed across a very wide range of mass-volume SoCs.
 122
 123 One very useful side-effect for example of a variable Power Domain voltage
 124 on a GPIO bank containing SD/MMC functionality is to be able to change the
 125 bank's voltage from 3.3v to 1.8v, to match an SD Card's capabilities, as
 126 permitted under the SD/MMC Specification.  The alternative is to be forced to
 127 deploy an external level-shifter IC (if PCB space and BOM target allows) or to
 128 fix the voltage at 3.3v and thus lose access to the low-power and higher-speed
 129 capabilities of modern SD Cards.
 130
 131 In summary: putting level shifters right at the I/O pads of the SoC, after
 132 the pin-mux (so that the core logic remains at the core voltage) is a
 133 cost-effective solution that can have additional unintended side-benefits
 134 and cost savings beyond simply saving on external level-shifting components
 135 and board space.
 136