shakti/m_class/pinmux.mdwn

   1 # Pin Multiplexing
   2
   3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=8>
   4 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   5   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   6   is a Watchdog Timer and others.
   7 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   8   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
   9
  10 Surprisingly complex!
  11
  12 # Requirements
  13
  14 "to create a general-purpose libre-licensed pinmux
  15 module that can be used with a wide range of interfaces that have
  16 Open-Drain, Push-Push *and bi-directional* capabilities, as well as
  17 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
  18 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
  19 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
  20
  21 ## Analysis
  22
  23 Questions:
  24
  25 * Can damage occur (to the ASIC) by outputs being short-circuited to outputs
  26   in any way?
  27   A partial analysis showed that because outputs are one-to-many, there should
  28   not be a possibility for that to occur.  However what if a function is
  29   bi-directional?
  30 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
  31   to be only done on EINT?
  32 * Can the input mux be turned round and "selector" logic added so that
  33   there is no possibility of damage to inputs?
  34
  35 # Images
  36
  37 * [[mygpiomux.jpg]
  38
  39 # GSoC2018
  40
  41 Introductions:
  42
  43 * Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
  44   advocate, assembly-level programming and disassembly, python, c, c++,
  45   gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
  46   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
  47   and currently responsible for coordinating the design of a fully Libre
  48   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
  49   not much experience at verilog (have done a couple of tutorials).
  50 * Xing GUO(xing) - undergraduate (3rd year) from Southeast
  51   University, EE student, C/C++, Python, Verilog, assembly (not very proficient),
  52   Haskell (not very proficient). RTL design, server maintenance.
  53   E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
  54 * Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
  55   at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
  56   Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
  57
  58 Hardware available:
  59
  60 * lkcl: ZC706
  61 * xing: zynq-7020 and Xilinx XC7A100T-484
  62
  63 # Discussion and Links
  64
  65 * <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
  66 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
  67 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
  68
  69 # Pinouts Specification
  70
  71 Covered in [[pinouts]].  The general idea is to target several
  72 distinct applications and, by trial-and-error, create a pinmux table that
  73 successfully covers all the target scenarios by providing absolutely all
  74 required functions for each and every target.  A few general rules:
  75
  76 * Different functions (SPI, I2C) which overlap on the same pins on one
  77  bank should also be duplicated on completely different banks, both from
  78  each other and also the bank on which they overlap.  With each bank having
  79  separate Power Domains this strategy increases the chances of being able
  80  to place low-power and high-power peripherals and sensors on separate
  81  GPIO banks without needing external level-shifters.
  82 * Functions which have optional bus-widths (eMMC: 1/2/4/8) may have more
  83  functions overlapping them than would otherwise normally be considered.
  84 * Then the same overlapped high-order bus pins can also be mapped onto
  85  other pins.  This particularly applies to the very large buses, such
  86  as FlexBus (over 50 pins).  However if the overlapped pins are on a
  87  different bank it becomes necessary to have both banks run in the same
  88  GPIO Power Domain.
  89 * All functions should really be pin-muxed at least twice, preferably
  90  three times.  Four or more times on average makes it pointless to
  91  even have four-way pinmuxing at all, so this should be avoided.
  92  The only exceptions (functions which have not been pinmuxed multiple
  93  times) are the RGB/TTL LCD channel, and both ULPI interfaces.
  94
  95 # GPIO Pinmux Power Domains
  96
  97 Of particular importance is the Power Domains for the GPIO.  Realistically
  98 it has to be flexible (simplest option: recommended to be between
  99 1.8v and 3.3v) as the majority of low-cost mass-produced sensors and
 100 peripherals on I2C, SPI, UART and SD/MMC are at or are compatible with
 101 this voltage range.  Long-tail (older / stable / low-cost / mass-produced)
 102 peripherals in particular tend to be 3.3v, whereas newer ones with a
 103 particular focus on Mobile tend to be 1.2v to 1.8v.
 104
 105 A large percentage of sensors and peripherals have separate IO voltage
 106 domains from their main supply voltage: a good example is the SN75LVDS83b
 107 which has one power domain for the RGB/TTL I/O, one for the LVDS output,
 108 and one for the internal logic controller (typical deployments tend not
 109 to notice the different power-domain capability, as they usually supply all
 110 three voltages at 3.3v).
 111
 112 Relying on this capability, however, by selecting a fixed voltage for
 113 the entire SoC's GPIO domain, is simply not a good idea: all sensors
 114 and peripherals which do not have a variable (VREF) capability for the
 115 logic side, or coincidentally are not at the exact same fixed voltage,
 116 will simply not be compatible if they are high-speed CMOS-level push-push
 117 driven.  Open-Drain on the other hand can be handled with a MOSFET for
 118 two-way or even a diode for one-way depending on the levels, but this means
 119 significant numbers of external components if the number of lines is large.
 120
 121 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 122 problem: external level-shifting is required on pretty much absolutely every
 123 single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
 124 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 125 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 126 worth of level-shifting, which is not just costly
 127 but also a huge amount of PCB space: bear in mind that for level-shifting, an
 128 IC with **double** the number of pins being level-shifted is required.
 129
 130 Given that level-shifting is an unavoidable necessity, and external
 131 level-shifting has such high cost(s), the workable solution is to
 132 actually include GPIO-group level-shifting actually on the SoC die,
 133 after the pin-muxer at the front-end (on the I/O pads of the die),
 134 on a per-bank basis.  This is an extremely common technique that is
 135 deployed across a very wide range of mass-volume SoCs.
 136
 137 One very useful side-effect for example of a variable Power Domain voltage
 138 on a GPIO bank containing SD/MMC functionality is to be able to change the
 139 bank's voltage from 3.3v to 1.8v, to match an SD Card's capabilities, as
 140 permitted under the SD/MMC Specification.  The alternative is to be forced to
 141 deploy an external level-shifter IC (if PCB space and BOM target allows) or to
 142 fix the voltage at 3.3v and thus lose access to the low-power and higher-speed
 143 capabilities of modern SD Cards.
 144
 145 In summary: putting level shifters right at the I/O pads of the SoC, after
 146 the pin-mux (so that the core logic remains at the core voltage) is a
 147 cost-effective solution that can have additional unintended side-benefits
 148 and cost savings beyond simply saving on external level-shifting components
 149 and board space.
 150