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[libreriscv.git] / shakti / m_class / sdram.mdwn
1 # SDRAM
2
3 * <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master>
4 * <https://opencores.org/projects/sdr_ctrl>
5 * WIP <https://gitlab.com/jock_tanner/asceticore/-/blob/master/control.py#L24-31>
6 * simulation verilator https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp
7 * breakout board for FPGA
8 - <https://rlx.sk/en/breakout-boards-shields/5155-sdram-board-b-waveshare-8mx16bit-sdram-h57v1262gtr.html>
9 - <https://rarecomponents.com/store/sdram-board-b>
10 - <https://hackaday.io/project/20053-anacon-xc/log/54443-sdram-breakout-board-designed>