Add verilog implementation of displayport
[libreriscv.git] / shakti / m_class / todo.mdwn
1 # TODO list summary
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3 Issues tracked on <http://bugs.libre-riscv.org>
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5 [[shakti_libre_riscv.jpg]]
6
7 ## RISC-V team
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9 * RV64GC SMP Core
10 * Analyse and decide L1 / L2 cache sizes (*underway*)
11 * Quad SPI (down-compatible to 1-bit SPI) (*done*) [[QSPI]]
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13 ## Richard Herveille
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15 * RGB/TTL interface, AXI conversion
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17 ## Rudi @ asics.ws
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19 * AC97/I2S/PCM interface
20 * DDR (4-bit) UTMI-to-ULPI
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22 ## TBD
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24 * 1/2/4-bit SD/MMC (Rudi?)
25 * eMMC (8-bit SD/MMC) (Rudi?)
26 * DDR3/DDR4 PHY
27 * Pinmux (underway)
28 * Video Processing Block
29 * 3D Engine (Nyuzi?)
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