simple_v_extension/daxpy_example.mdwn

   1 # c code
   2
   3 ```
   4     void daxpy(size_t n, double a, const double x[], double y[]) {
   5         for (size_t i = 0; i < n; i++)
   6             y[i] = a*x[i] + y[i];
   7     }
   8 ```
   9
  10 # SVP64 Power ISA version
  11
  12 Summary: 9 instructions (see below, 8 instructions) 5 of which are 64-bit
  13 for a total of 14 "words".
  14
  15 ```
  16     # r5: n count; r6: x ptr; r7: y ptr; fp1: a
  17     1  mtctr 5                # move n to CTR
  18     2  addi r10,r6,0          # copy y-ptr into r10 (y')
  19     3  .L2
  20     4  setvl MAXVL=32,VL=CTR  # actually VL=MIN(MAXVL,CTR)
  21     5  sv.lfdup *32,8(6)      # load x into fp32-63, inc x
  22     6  sv.lfdup *64,8(7)      # load y into fp64-95, inc y
  23     7  sv.fmadd *64,*64,1,*32 # (*y) = (*y) * (*x) + fp1
  24     8  sv.stfdup *64,8(10)    # store at y-copy, inc y'
  25     9  sv.bc/ctr .L2          # decr CTR by VL, jump !zero
  26     10 blr                    # return
  27 ```
  28
  29 A refinement, reducing 1 instruction and register port usage.
  30 Relies on post-increment, relies on no overlap between x and y
  31 in memory, and critically relies on y overwrite.
  32
  33 ```
  34     # r5: n count; r6: x ptr; r7: y ptr; fp1: a
  35     1  mtctr 5                # move n to CTR
  36     2  .L2
  37     3  setvl MAXVL=32,VL=CTR  # actually VL=MIN(MAXVL,CTR)
  38     4  sv.lfdup *32,8(6)      # load x into fp32-63, incr x
  39     5  sv.lfd *64,8(7)        # load y into fp64-95, NO INC
  40     6  sv.fmadd *64,*64,1,*32 # (*y) = (*y) * (*x) + fp1
  41     7  sv.stfdup *64,8(7)     # store at y, incr y
  42     8  sv.bc/ctr .L2          # decr CTR by VL, jump !zero
  43     9  blr                    # return
  44 ```
  45
  46 # RVV version
  47
  48 Summary: 12 instructions, 7 32-bit and 5 16-bit for a total of 9.5 "words"
  49
  50 ```
  51     # a0 is n, a1 is pointer to x[0], a2 is pointer to y[0], fa0 is a
  52       li t0, 2<<25
  53       vsetdcfg t0             # enable 2 64b Fl.Pt. registers
  54     loop:
  55       setvl  t0, a0           # vl = t0 = min(mvl, n)
  56       vld    v0, a1           # load vector x
  57       c.slli   t1, t0, 3      # t1 = vl * 8 (in bytes)
  58       vld    v1, a2           # load vector y
  59       c.add    a1, a1, t1     # increment pointer to x by vl*8
  60       vfmadd v1, v0, fa0, v1  # v1 += v0 * fa0 (y = a * x + y)
  61       c.sub    a0, a0, t0     # n -= vl (t0)
  62       vst    v1, a2           # store Y
  63       c.add    a2, a2, t1     # increment pointer to y by vl*8
  64       c.bnez   a0, loop       # repeat if n != 0
  65       c.ret                   # return
  66 ```
  67
  68 # SVE Version
  69
  70 Summary: 12 instructions, all 32-bit, for a total of 12 "words"
  71
  72 ```
  73     1  // x0 = &x[0], x1 = &y[0], x2 = &a, x3 = &n
  74     2  daxpy_:
  75     3  ldrswx3, [x3]                     // x3=*n
  76     4  movx4, #0                         // x4=i=0
  77     5  whilelt p0.d, x4, x3              // p0=while(i++<n)
  78     6  ld1rdz0.d, p0/z, [x2]             // p0:z0=bcast(*a)
  79     7  .loop:
  80     8  ld1d z1.d, p0/z, [x0, x4, lsl #3] // p0:z1=x[i]
  81     9  ld1d z2.d, p0/z, [x1, x4, lsl #3] // p0:z2=y[i]
  82     10 fmla z2.d, p0/m, z1.d, z0.d       // p0?z2+=x[i]*a
  83     11 st1d z2.d, p0, [x1, x4, lsl #3]   // p0?y[i]=z2
  84     12 incd x4                           // i+=(VL/64)
  85     13 .latch:
  86     14 whilelt p0.d, x4, x3             // p0=while(i++<n)
  87     15 b.first .loop                    // more to do?
  88     16 ret
  89 ```