1 # SimpleV Instruction Categorisation
3 Based on information from Michael Clark's riscv-meta opcodes table
4 (with thanks to Michael for creating it), this
5 page categorises and identifies the type of parallelism that SimpleV
6 indirectly adds on each RISC-V **standard** opcode. These are note-form:
7 see [[specification]] for full details.
9 Note that the list is necessarily incomplete, as any custom or future
10 extensions may also benefit from fitting one of the categories below.
12 * **-** no change of behaviour takes place: operation remains
13 **completely scalar** as an **unmodified**, unaugmented standard RISC-V
14 opcode, even if it has registers.
15 * **sv** - a standard contiguous (optionally predicated, optionally
16 indirected) multi-register operation where the predication register
17 to be used for the sequence of contiguous operations is taken from the
18 **destination** register's predication lookup entry.
19 * **2v** - a standard contiguous (optionally twin-predicated, optionally
20 indirected) twin-register operation (distinct source and destination)
21 where either or both of source or destination may be redirected,
22 vectorised, or **independently** predicated. This behaviour
23 covers the *entire* VMV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
25 * **vld** - a standard contiguous (optionally twin-predicated, optionally
26 indirected) multi-register load operation where either or both of
27 destination register or load-from-address register may be redirected,
28 vectorised or **independently** predicated (LD.X style functionality).
29 (*Note: Vector "Unit Stride" and "Constant Stride" may be emulated by
30 pre-prepping a contiguous block of load-from-address registers with
31 the appropriate address offsets*)
32 * **vst** - a matching multi-register store operation with orthogonal
33 functionality to **vld**.
34 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
35 source-address register number being (optionally) incremented
36 (and redirected, and predicated) it is the **immediate offset**
37 that is incremented (by the element width of the **source** register)
38 * **VSU** - a similarly "Unit Strided" variant of **vst**.
39 * **VBR** - a standard branch operation (optionally predicated, optionally
40 indirected) multi-register operation where the (optional) predication for the
41 compare is taken from the destination register, and where (optionally)
42 if the results of the multi-comparison are to be recorded, the **source**
43 register's predication table entry is used as the means to specify
44 (in a bitfield format that is directly compatible for follow-up use as a
45 predicate) the register in which the comparison results are stored.
46 On completion of all compares, if the tests carried out succeeded
47 (de-predicated compares not being included in this assessment, evidently),
48 the branch operation is carried out.
50 # RV32I/RV64I/RV128I "RV32I/RV64I/RV128I Base Integer Instruction Set"
52 | (23..18) | (17..12) | (11..6) | (5...0) | |
53 | -------- | -------- | ------- | ------- | |
54 |auipc | rd oimm20 | u+o | rv32i rv64i rv128i | - |
55 |jal | rd jimm20 | uj | rv32i rv64i rv128i | - |
56 |jalr | rd rs1 oimm12 | i+o | rv32i rv64i rv128i | - |
57 |fence | | r·f | rv32i rv64i rv128i | - |
58 |fence.i | | none | rv32i rv64i rv128i | - |
60 |lui | rd imm20 | u | rv32i rv64i rv128i | sv |
62 |beq | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
63 |bne | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
64 |blt | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
65 |bge | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
66 |bltu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
67 |bgeu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
69 |lb | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
70 |lh | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
71 |lw | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
72 |lbu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
73 |lhu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
74 |lwu | rd rs1 oimm12 | i+l | rv64i rv128i | vld |
75 |ld | rd rs1 oimm12 | i+l | rv64i rv128i | vld |
76 |ldu | rd rs1 oimm12 | i+l | rv128i | vld |
77 |lq | rd rs1 oimm12 | i+l | rv128i | vld |
79 |sb | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
80 |sh | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
81 |sw | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
82 |sd | rs1 rs2 simm12 | s | rv64i rv128i | vst |
83 |sq | rs1 rs2 simm12 | s | rv128i | vst |
85 |addi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
86 |slti | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
87 |sltiu | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
88 |xori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
89 |ori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
90 |andi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
91 |slli | rd rs1 shamt5 | i·sh5 | rv32i | sv |
92 |srli | rd rs1 shamt5 | i·sh5 | rv32i | sv |
93 |srai | rd rs1 shamt5 | i·sh5 | rv32i | sv |
94 |add | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
95 |sub | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
96 |sll | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
97 |slt | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
98 |sltu | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
99 |xor | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
100 |srl | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
101 |sra | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
102 |or | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
103 |and | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
104 |slli | rd rs1 shamt6 | i·sh6 | rv64i | sv |
105 |srli | rd rs1 shamt6 | i·sh6 | rv64i | sv |
106 |srai | rd rs1 shamt6 | i·sh6 | rv64i | sv |
107 |addiw | rd rs1 imm12 | i | rv64i rv128i | sv |
108 |slliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
109 |srliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
110 |sraiw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
111 |addw | rd rs1 rs2 | r | rv64i rv128i | sv |
112 |subw | rd rs1 rs2 | r | rv64i rv128i | sv |
113 |sllw | rd rs1 rs2 | r | rv64i rv128i | sv |
114 |srlw | rd rs1 rs2 | r | rv64i rv128i | sv |
115 |sraw | rd rs1 rs2 | r | rv64i rv128i | sv |
116 |slli | rd rs1 shamt7 | i·sh7 | rv128i | sv |
117 |srli | rd rs1 shamt7 | i·sh7 | rv128i | sv |
118 |srai | rd rs1 shamt7 | i·sh7 | rv128i | sv |
119 |addid | rd rs1 imm12 | i | rv128i | sv |
120 |sllid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
121 |srlid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
122 |sraid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
123 |addd | rd rs1 rs2 | r | rv128i | sv |
124 |subd | rd rs1 rs2 | r | rv128i | sv |
125 |slld | rd rs1 rs2 | r | rv128i | sv |
126 |srld | rd rs1 rs2 | r | rv128i | sv |
127 |srad | rd rs1 rs2 | r | rv128i | sv |
129 # RV32M "RV32M Standard Extension for Integer Multiply and Divide"
131 | (23..18) | (17..12) | (11..6) | (5...0) | |
132 | -------- | -------- | ------- | ------- | |
133 |mul | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
134 |mulh | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
135 |mulhsu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
136 |mulhu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
137 |div | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
138 |divu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
139 |rem | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
140 |remu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
142 # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
144 | (23..18) | (17..12) | (11..6) | (5...0) | |
145 | -------- | -------- | ------- | ------- | |
146 |mulw | rd rs1 rs2 | r | rv64m rv128m | sv |
147 |divw | rd rs1 rs2 | r | rv64m rv128m | sv |
148 |divuw | rd rs1 rs2 | r | rv64m rv128m | sv |
149 |remw | rd rs1 rs2 | r | rv64m rv128m | sv |
150 |remuw | rd rs1 rs2 | r | rv64m rv128m | sv |
152 # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
154 | (23..18) | (17..12) | (11..6) | (5...0) | |
155 | -------- | -------- | ------- | ------- | |
156 |muld | rd rs1 rs2 | r | rv128m | sv |
157 |divd | rd rs1 rs2 | r | rv128m | sv |
158 |divud | rd rs1 rs2 | r | rv128m | sv |
159 |remd | rd rs1 rs2 | r | rv128m | sv |
160 |remud | rd rs1 rs2 | r | rv128m | sv |
162 # RV32A "RV32A Standard Extension for Atomic Instructions"
164 | (23..18) | (17..12) | (11..6) | (5...0) | |
165 | -------- | -------- | ------- | ------- | |
166 |lr.w | rd rs1 | r·l | rv32a rv64a rv128a | - |
167 |sc.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | - |
169 |amoswap.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
170 |amoadd.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
171 |amoxor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
172 |amoor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
173 |amoand.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
174 |amomin.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
175 |amomax.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
176 |amominu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
177 |amomaxu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
179 # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
181 | (23..18) | (17..12) | (11..6) | (5...0) | |
182 | -------- | -------- | ------- | ------- | |
183 |lr.d | rd rs1 | r·l | rv64a rv128a | - |
184 |sc.d | rd rs1 rs2 | r·a | rv64a rv128a | - |
186 |amoswap.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
187 |amoadd.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
188 |amoxor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
189 |amoor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
190 |amoand.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
191 |amomin.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
192 |amomax.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
193 |amominu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
194 |amomaxu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
196 # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
198 | (23..18) | (17..12) | (11..6) | (5...0) | |
199 | -------- | -------- | ------- | ------- | |
200 |lr.q | rd rs1 | r·l | rv128a | - |
201 |sc.q | rd rs1 rs2 | r·a | rv128a | - |
203 |amoswap.q| rd rs1 rs2 | r·a | rv128a | sv |
204 |amoadd.q | rd rs1 rs2 | r·a | rv128a | sv |
205 |amoxor.q | rd rs1 rs2 | r·a | rv128a | sv |
206 |amoor.q | rd rs1 rs2 | r·a | rv128a | sv |
207 |amoand.q | rd rs1 rs2 | r·a | rv128a | sv |
208 |amomin.q | rd rs1 rs2 | r·a | rv128a | sv |
209 |amomax.q | rd rs1 rs2 | r·a | rv128a | sv |
210 |amominu.q| rd rs1 rs2 | r·a | rv128a | sv |
211 |amomaxu.q| rd rs1 rs2 | r·a | rv128a | sv |
213 # RV32S "RV32S Standard Extension for Supervisor-level Instructions"
215 | (23..18) | (17..12) | (11..6) | (5...0) | |
216 | -------- | -------- | ------- | ------- | |
217 |ecall | | none | rv32s rv64s rv128s | - |
218 |ebreak | | none | rv32s rv64s rv128s | - |
219 |uret | | none | rv32s rv64s rv128s | - |
220 |sret | | none | rv32s rv64s rv128s | - |
221 |hret | | none | rv32s rv64s rv128s | - |
222 |mret | | none | rv32s rv64s rv128s | - |
223 |dret | | none | rv32s rv64s rv128s | - |
224 |sfence.vm | rs1 | r+sf | rv32s rv64s rv128s | - |
225 |sfence.vma| rs1 rs2 | r+sfa | rv32s rv64s rv128s | - |
226 |wfi | | none | rv32s rv64s rv128s | - |
228 |csrrw | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
229 |csrrs | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
230 |csrrc | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
231 |csrrwi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
232 |csrrsi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
233 |csrrci | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
235 # RV32F "RV32F Standard Extension for Single-Precision Floating-Point"
237 | (23..18) | (17..12) | (11..6) | (5...0) | |
238 | -------- | -------- | ------- | ------- | |
239 |flw | frd rs1 oimm12 | i+lf | rv32f rv64f rv128f | vld |
240 |fsw | rs1 frs2 simm12 | s+f | rv32f rv64f rv128f | vld |
242 |fmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
243 |fmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
244 |fnmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
245 |fnmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
246 |fadd.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
247 |fsub.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
248 |fmul.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
249 |fdiv.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
250 |fmin.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv |
251 |fmax.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv |
252 |fsqrt.s | frd frs1 rm | r·m+ff | rv32f rv64f rv128f | sv |
253 |fle.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
254 |flt.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
255 |feq.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
256 |fclass.s | rd frs1 | r+rf | rv32f rv64f rv128f | sv |
257 |fsgnj.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
258 |fsgnjn.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
259 |fsgnjx.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
260 |fcvt.w.s | rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v |
261 |fcvt.wu.s| rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v |
262 |fcvt.s.w | frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v |
263 |fcvt.s.wu| frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v |
264 |fmv.x.s | rd frs1 | r+rf | rv32f rv64f rv128f | 2v |
265 |fmv.s.x | frd rs1 | r+fr | rv32f rv64f rv128f | 2v |
267 # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
269 | (23..18) | (17..12) | (11..6) | (5...0) | |
270 | -------- | -------- | ------- | ------- | |
271 |fcvt.l.s | rd frs1 rm | r·m+rf | rv64f rv128f | 2v |
272 |fcvt.lu.s| rd frs1 rm | r·m+rf | rv64f rv128f | 2v |
273 |fcvt.s.l | frd rs1 rm | r·m+fr | rv64f rv128f | 2v |
274 |fcvt.s.lu| frd rs1 rm | r·m+fr | rv64f rv128f | 2v |
276 # RV32D "RV32D Standard Extension for Double-Precision Floating-Point"
278 | (23..18) | (17..12) | (11..6) | (5...0) | |
279 | -------- | -------- | ------- | ------- | |
280 |fld | frd rs1 oimm12 | i+lf | rv32d rv64d rv128d | vld |
281 |fsd | rs1 frs2 simm12 | s+f | rv32d rv64d rv128d | vld |
283 |fmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
284 |fmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
285 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
286 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
287 |fadd.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
288 |fsub.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
289 |fmul.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
290 |fdiv.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
291 |fmin.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv |
292 |fmax.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv |
293 |fsqrt.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | sv |
294 |fle.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
295 |flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
296 |feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
297 |fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | sv |
299 |fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
300 |fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
301 |fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
302 |fcvt.s.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v |
303 |fcvt.d.s | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v |
304 |fcvt.w.d | rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v |
305 |fcvt.wu.d| rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v |
306 |fcvt.d.w | frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v |
307 |fcvt.d.wu| frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v |
309 # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
311 | (23..18) | (17..12) | (11..6) | (5...0) | |
312 | -------- | -------- | ------- | ------- | |
313 |fcvt.l.d | rd frs1 rm | r·m+rf | rv64d rv128d | 2v |
314 |fcvt.lu.d| rd frs1 rm | r·m+rf | rv64d rv128d | 2v |
315 |fmv.x.d | rd frs1 | r+rf | rv64d rv128d | 2v |
316 |fcvt.d.l | frd rs1 rm | r·m+fr | rv64d rv128d | 2v |
317 |fcvt.d.lu| frd rs1 rm | r·m+fr | rv64d rv128d | 2v |
318 |fmv.d.x | frd rs1 | r+fr | rv64d rv128d | 2v |
320 # RV32Q "RV32Q Standard Extension for Quad-Precision Floating-Point"
322 | (23..18) | (17..12) | (11..6) | (5...0) | |
323 | -------- | -------- | ------- | ------- | |
324 |flq | frd rs1 oimm12 | i+lf | rv32q rv64q rv128q | vld |
326 |fsq | rs1 frs2 simm12 | s+f | rv32q rv64q rv128q | vst |
328 |fmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
329 |fmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
330 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
331 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
332 |fadd.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
333 |fsub.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
334 |fmul.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
335 |fdiv.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
336 |fmin.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv |
337 |fmax.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv |
338 |fsqrt.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | sv |
339 |fle.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
340 |flt.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
341 |feq.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
342 |fclass.q | rd frs1 | r+rf | rv32q rv64q rv128q | sv |
344 |fsgnj.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
345 |fsgnjn.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
346 |fsgnjx.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
347 |fcvt.s.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
348 |fcvt.q.s | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
349 |fcvt.d.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
350 |fcvt.q.d | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
351 |fcvt.w.q | rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v |
352 |fcvt.wu.q| rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v |
353 |fcvt.q.w | frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v |
354 |fcvt.q.wu| frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v |
356 # RV64Q "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
358 | (23..18) | (17..12) | (11..6) | (5...0) | |
359 | -------- | -------- | ------- | ------- | |
360 |fcvt.l.q | rd frs1 rm | r·m+rf | rv64q rv128q | 2v |
361 |fcvt.lu.q| rd frs1 rm | r·m+rf | rv64q rv128q | 2v |
362 |fcvt.q.l | frd rs1 rm | r·m+fr | rv64q rv128q | 2v |
363 |fcvt.q.lu| frd rs1 rm | r·m+fr | rv64q rv128q | 2v |
365 # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
367 | (23..18) | (17..12) | (11..6) | (5...0) | |
368 | -------- | -------- | ------- | ------- | |
369 |fmv.x.q | rd frs1 | r+rf | rv64q rv128q | 2v |
370 |fmv.q.x | frd rs1 | r+fr | rv64q rv128q | 2v |
372 # RV32C/RV64C/RV128C "RV32C/RV64C/RV128C Standard Extension for Compressed Instructions"
374 | (23..18) | (17..12) | (11..6) | (5...0) | |
375 | -------- | -------- | ------- | ------- | |
376 |c.addi4spn|crdq cimm4spn | ciw·4spn | rv32c rv64c | - |
377 |c.nop | | ci·none | rv32c rv64c | - |
378 |c.jal | cimmj | cj·jal | rv32c | - |
379 |c.j | cimmj | cj | rv32c rv64c | - |
380 |c.jr | crd0 crs1 | cr·jr | rv32c rv64c | - |
381 |c.ebreak | | ci·none | rv32c rv64c | - |
382 |c.jalr | crd0 crs1 | cr·jalr | rv32c rv64c | - |
384 |c.mv | crd crs2 | cr·mv | rv32c rv64c | 2v |
386 |c.fld | cfrdq crs1q cimmd | cl·ld+f | rv32c rv64c | vld |
387 |c.lw | crdq crs1q cimmw | cl·lw | rv32c rv64c | vld |
388 |c.flw | cfrdq crs1q cimmw | cl·lw+f | rv32c | vld |
389 |c.ld | crdq crs1q cimmd | cl·ld | rv64c | vld |
390 |c.lq | crdq crs1q cimmq | cl·lq | rv128c | vld |
392 |c.fsd | crs1q cfrs2q cimmd | cs·sd+f | rv32c rv64c | vst |
393 |c.sw | crs1q crs2q cimmw | cs·sw | rv32c rv64c | vst |
394 |c.fsw | crs1q cfrs2q cimmw | cs·sw+f | rv32c | vst |
395 |c.sd | crs1q crs2q cimmd | cs·sd | rv64c | vst |
396 |c.sq | crs1q crs2q cimmq | cs·sq | rv128c | vst |
398 |c.addi16sp|crs1rd cimm16sp | ci·16sp | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) |
399 |c.addi | crs1rd cnzimmi | ci | rv32c rv64c | sv |
400 |c.li | crs1rd cimmi | ci·li | rv32c rv64c | sv |
401 |c.lui | crd cimmui | ci·lui | rv32c rv64c | sv |
402 |c.srli | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv |
403 |c.srai | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv |
404 |c.slli | crs1rd cimmsh5 | ci·sh5 | rv32c | sv |
405 |c.andi | crs1rdq cnzimmi | cb·imm | rv32c rv64c | sv |
406 |c.sub | crs1rdq crs2q | cs | rv32c rv64c | sv |
407 |c.xor | crs1rdq crs2q | cs | rv32c rv64c | sv |
408 |c.or | crs1rdq crs2q | cs | rv32c rv64c | sv |
409 |c.and | crs1rdq crs2q | cs | rv32c rv64c | sv |
410 |c.subw | crs1rdq crs2q | cs | rv32c rv64c | sv |
411 |c.addw | crs1rdq crs2q | cs | rv32c rv64c | sv |
412 |c.add | crs1rd crs2 | cr | rv32c rv64c | sv |
413 |c.addiw | crs1rd cimmi | ci | rv64c | sv |
414 |c.srli | crs1rdq cimmsh6 | cb·sh6 | rv64c | sv |
415 |c.srai | crs1rdq cimmsh6 | cb·sh6 | rv64c | sv |
416 |c.slli | crs1rd cimmsh6 | ci·sh6 | rv64c | sv |
418 |c.beqz | crs1q cimmb | cb | rv32c rv64c | VBR |
419 |c.bnez | crs1q cimmb | cb | rv32c rv64c | VBR |
421 |c.fldsp | cfrd cimmldsp | ci·ldsp+f | rv32c rv64c | VLU |
422 |c.lwsp | crd cimmlwsp | ci·lwsp | rv32c rv64c | VLU |
423 |c.flwsp | cfrd cimmlwsp | ci·lwsp+f | rv32c | VLU |
424 |c.ldsp | crd cimmldsp | ci·ldsp | rv64c | VLU |
425 |c.lqsp | crd cimmlqsp | ci·lqsp | rv128c | VLU |
427 |c.fsdsp | cfrs2 cimmsdsp | css·sdsp+f | rv32c rv64c | VSU |
428 |c.swsp | crs2 cimmswsp | css·swsp | rv32c rv64c | VSU |
429 |c.fswsp | cfrs2 cimmswsp | css·swsp+f | rv32c | VSU |
430 |c.sdsp | crs2 cimmsdsp | css·sdsp | rv64c | VSU |
431 |c.sqsp | crs2 cimmsqsp | css·sqsp | rv128c | VSU |
projects / libreriscv.git / blob