simple_v_extension/opcodes.mdwn

   1 # SimpleV Instruction Categorisation
   2
   3 Based on information from Michael Clark's riscv-meta opcodes table, this
   4 page categorises and identifies the type of parallelism that SimpleV
   5 indirectly adds on each RISC-V **standard** opcode.
   6
   7 * **-** no change of behaviour takes place: operation remains
   8   **completely scalar** even if it has registers.
   9 * **sv** - a standard contiguous (optionally predicated, optionally
  10   indirected) multi-register operation where the predication for
  11   the operation is taken from the **destination** register
  12 * **2v** - a standard contiguous (optionally twin-predicated, optionally
  13   indirected) twin-register operation (distinct source and destination)
  14   where either or both of source or destination may be redirected,
  15   vectorised, or **independently** predicated.  This behaviour
  16   covers the **entire** VMV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
  17   paradigm.
  18 * **vld** - a standard contiguous (optionally twin-predicated, optionally
  19   indirected) multi-register load operation where either or both of
  20   destination register or load-from-address register may be redirected,
  21   vectorised or **independently** predicated.
  22 * **vst** - a matching multi-register store operation matching **vld**.
  23 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
  24   source-address register number being (optionally) incremented
  25   (and redirected, and predicated) it is the **immediate offset**
  26   that is incremented (by the element width of the **source** register)
  27 * **VSU** - a similarly "Unit Stride" variant of **vst**.
  28 * **VBR** - a standard branch operation (optionally predicated, optionally
  29   indirected) multi-register option where the (optional) predication for the
  30   compare is taken from the destination register, and where (optionally)
  31   if the results of the multi-comparison are to be recorded, the **source**
  32   register's predication target is used.  On completion of all compares,
  33   if the tests carried out succeeded (de-predicated compares not being included
  34   in this assessment), the branch operation is carried out.
  35
  36 # RV32I/RV64I/RV128I    "RV32I/RV64I/RV128I Base Integer Instruction Set"
  37
  38 | (23..18) | (17..12) | (11..6) | (5...0) |  |
  39 | -------- | -------- | ------- | ------- |  |
  40 |auipc    | rd oimm20       | u+o  | rv32i rv64i rv128i | -  |
  41 |jal      | rd jimm20       | uj   | rv32i rv64i rv128i | -  |
  42 |jalr     | rd rs1 oimm12   | i+o  | rv32i rv64i rv128i | -  |
  43 |fence    |                 | r·f | rv32i rv64i rv128i | -  |
  44 |fence.i  |                 | none | rv32i rv64i rv128i | -  |
  45 |lui      | rd imm20        | u     | rv32i rv64i rv128i | sv  |
  46 |beq      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  47 |bne      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  48 |blt      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  49 |bge      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  50 |bltu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  51 |bgeu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  52 |lb       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  53 |lh       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  54 |lw       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  55 |lbu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  56 |lhu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  57 |lwu      | rd rs1 oimm12   |  i+l        | rv64i rv128i | vld  |
  58 |ld       | rd rs1 oimm12   |  i+l        | rv64i rv128i | vld  |
  59 |ldu      | rd rs1 oimm12  |   i+l              | rv128i | vld  |
  60 |lq       | rd rs1 oimm12  |   i+l              | rv128i | vld  |
  61 |sb       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  62 |sh       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  63 |sw       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  64 |sd       | rs1 rs2 simm12  |  s          | rv64i rv128i | vst  |
  65 |sq       | rs1 rs2 simm12 |   s                | rv128i | vst  |
  66 |addi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  67 |slti     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  68 |sltiu    | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  69 |xori     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  70 |ori      | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  71 |andi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  72 |slli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  73 |srli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  74 |srai     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  75 |add      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  76 |sub      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  77 |sll      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  78 |slt      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  79 |sltu     | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  80 |xor      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  81 |srl      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  82 |sra      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  83 |or       | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  84 |and      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  85 |slli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  86 |srli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  87 |srai     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  88 |addiw    | rd rs1 imm12    |  i          | rv64i rv128i | sv  |
  89 |slliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  90 |srliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  91 |sraiw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  92 |addw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  93 |subw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  94 |sllw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  95 |srlw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  96 |sraw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  97 |slli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
  98 |srli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
  99 |srai     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
 100 |addid    | rd rs1 imm12   |   i                | rv128i | sv  |
 101 |sllid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 102 |srlid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 103 |sraid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 104 |addd     | rd rs1 rs2     |   r                | rv128i | sv  |
 105 |subd     | rd rs1 rs2     |   r                | rv128i | sv  |
 106 |slld     | rd rs1 rs2     |   r                | rv128i | sv  |
 107 |srld     | rd rs1 rs2     |   r                | rv128i | sv  |
 108 |srad     | rd rs1 rs2     |   r                | rv128i | sv  |
 109
 110 # RV32M    "RV32M Standard Extension for Integer Multiply and Divide"
 111
 112 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 113 | -------- | -------- | ------- | ------- |  |
 114 |mul      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 115 |mulh     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 116 |mulhsu   | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 117 |mulhu    | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 118 |div      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 119 |divu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 120 |rem      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 121 |remu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 122
 123 # RV64M    "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
 124
 125 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 126 | -------- | -------- | ------- | ------- |  |
 127 |mulw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 128 |divw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 129 |divuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 130 |remw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 131 |remuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 132
 133 # RV128M   "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
 134
 135 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 136 | -------- | -------- | ------- | ------- |  |
 137 |muld     | rd rs1 rs2   |     r                | rv128m | sv  |
 138 |divd     | rd rs1 rs2   |     r                | rv128m | sv  |
 139 |divud    | rd rs1 rs2   |     r                | rv128m | sv  |
 140 |remd     | rd rs1 rs2   |     r                | rv128m | sv  |
 141 |remud    | rd rs1 rs2   |     r                | rv128m | sv  |
 142
 143 # RV32A    "RV32A Standard Extension for Atomic Instructions"
 144
 145 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 146 | -------- | -------- | ------- | ------- |  |
 147 |lr.w     | rd rs1          | r·l | rv32a rv64a rv128a | -  |
 148 |sc.w     | rd rs1 rs2      | r·a | rv32a rv64a rv128a | -  |
 149 |amoswap.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 150 |amoadd.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 151 |amoxor.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 152 |amoor.w  | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 153 |amoand.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 154 |amomin.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 155 |amomax.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 156 |amominu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 157 |amomaxu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 158
 159 # RV64A    "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
 160
 161 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 162 | -------- | -------- | ------- | ------- |  |
 163 |lr.d     | rd rs1          | r·l      | rv64a rv128a | - |
 164 |sc.d     | rd rs1 rs2      | r·a      | rv64a rv128a | - |
 165 |amoswap.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 166 |amoadd.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 167 |amoxor.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 168 |amoor.d  | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 169 |amoand.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 170 |amomin.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 171 |amomax.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 172 |amominu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 173 |amomaxu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 174
 175 # RV128A   "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
 176
 177 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 178 | -------- | -------- | ------- | ------- |  |
 179 |lr.q     | rd rs1          | r·l | rv128a | - |
 180 |sc.q     | rd rs1 rs2      | r·a | rv128a | - |
 181 |amoswap.q| rd rs1 rs2      | r·a | rv128a | sv  |
 182 |amoadd.q | rd rs1 rs2      | r·a | rv128a | sv  |
 183 |amoxor.q | rd rs1 rs2      | r·a | rv128a | sv  |
 184 |amoor.q  | rd rs1 rs2      | r·a | rv128a | sv  |
 185 |amoand.q | rd rs1 rs2      | r·a | rv128a | sv  |
 186 |amomin.q | rd rs1 rs2      | r·a | rv128a | sv  |
 187 |amomax.q | rd rs1 rs2      | r·a | rv128a | sv  |
 188 |amominu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 189 |amomaxu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 190
 191 # RV32S    "RV32S Standard Extension for Supervisor-level Instructions"
 192
 193 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 194 | -------- | -------- | ------- | ------- |  |
 195 |ecall     |                         | none    | rv32s rv64s rv128s | - |
 196 |ebreak    |                         | none    | rv32s rv64s rv128s | - |
 197 |uret      |                         | none    | rv32s rv64s rv128s | - |
 198 |sret      |                         | none    | rv32s rv64s rv128s | - |
 199 |hret      |                         | none    | rv32s rv64s rv128s | - |
 200 |mret      |                         | none    | rv32s rv64s rv128s | - |
 201 |dret      |                         | none    | rv32s rv64s rv128s | - |
 202 |sfence.vm |         rs1             | r+sf    | rv32s rv64s rv128s | - |
 203 |sfence.vma| rs1 rs2                 | r+sfa   | rv32s rv64s rv128s | - |
 204 |wfi       |                         | none    | rv32s rv64s rv128s | - |
 205 |csrrw     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 206 |csrrs     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 207 |csrrc     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 208 |csrrwi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 209 |csrrsi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 210 |csrrci    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 211
 212 # RV32F    "RV32F Standard Extension for Single-Precision Floating-Point"
 213
 214 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 215 | -------- | -------- | ------- | ------- | |
 216 |flw      | frd rs1           oimm12      | i+lf  | rv32f rv64f rv128f | vld  |
 217 |fsw      | rs1 frs2          simm12      | s+f   | rv32f rv64f rv128f | vld  |
 218 |fmadd.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 219 |fmsub.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 220 |fnmsub.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 221 |fnmadd.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 222 |fadd.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 223 |fsub.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 224 |fmul.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 225 |fdiv.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 226 |fmin.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 227 |fmax.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 228 |fsqrt.s  | frd frs1                   rm | r·m+ff | rv32f rv64f rv128f | sv  |
 229 |fle.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 230 |flt.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 231 |feq.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 232 |fclass.s | rd frs1                       | r+rf  | rv32f rv64f rv128f | sv  |
 233 |fsgnj.s  | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 234 |fsgnjn.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 235 |fsgnjx.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 236 |fcvt.w.s | rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 237 |fcvt.wu.s| rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 238 |fcvt.s.w | frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 239 |fcvt.s.wu| frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 240 |fmv.x.s  | rd frs1                       | r+rf  | rv32f rv64f rv128f | 2v  |
 241 |fmv.s.x  | frd rs1                       | r+fr  | rv32f rv64f rv128f | 2v  |
 242
 243 # RV64F    "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
 244
 245 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 246 | -------- | -------- | ------- | ------- |  |
 247 |fcvt.l.s | rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 248 |fcvt.lu.s| rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 249 |fcvt.s.l | frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 250 |fcvt.s.lu| frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 251
 252 # RV32D    "RV32D Standard Extension for Double-Precision Floating-Point"
 253
 254 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 255 | -------- | -------- | ------- | ------- |  |
 256 |fld      | frd rs1   oimm12      | i+lf  | rv32d rv64d rv128d | vld  |
 257 |fsd      | rs1 frs2  simm12      | s+f   | rv32d rv64d rv128d | vld  |
 258 |fmadd.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 259 |fmsub.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 260 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 261 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 262 |fadd.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 263 |fsub.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 264 |fmul.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 265 |fdiv.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 266 |fmin.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 267 |fmax.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 268 |fsqrt.d  | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | sv  |
 269 |fle.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 270 |flt.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 271 |feq.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 272 |fclass.d | rd frs1               | r+rf  | rv32d rv64d rv128d | sv  |
 273 |fsgnj.d  | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 274 |fsgnjn.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 275 |fsgnjx.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 276 |fcvt.s.d | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 277 |fcvt.d.s | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 278 |fcvt.w.d | rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 279 |fcvt.wu.d| rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 280 |fcvt.d.w | frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 281 |fcvt.d.wu| frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 282
 283 # RV64D    "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
 284
 285 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 286 | -------- | -------- | ------- | ------- |  |
 287 |fcvt.l.d | rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 288 |fcvt.lu.d| rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 289 |fmv.x.d  | rd frs1          | r+rf        | rv64d rv128d | 2v  |
 290 |fcvt.d.l | frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 291 |fcvt.d.lu| frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 292 |fmv.d.x  | frd rs1          | r+fr        | rv64d rv128d | 2v  |
 293
 294 # RV32Q    "RV32Q Standard Extension for Quad-Precision Floating-Point"
 295
 296 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 297 | -------- | -------- | ------- | ------- |  |
 298 |flq      | frd rs1       oimm12  | i+lf   | rv32q rv64q rv128q | vld  |
 299 |fsq      | rs1 frs2      simm12  | s+f    | rv32q rv64q rv128q | vst  |
 300 |fmadd.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 301 |fmsub.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 302 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 303 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 304 |fadd.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 305 |fsub.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 306 |fmul.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 307 |fdiv.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 308 |fmin.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 309 |fmax.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 310 |fsqrt.q  | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | sv  |
 311 |fle.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 312 |flt.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 313 |feq.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 314 |fclass.q | rd frs1               | r+rf   | rv32q rv64q rv128q | sv  |
 315 |fsgnj.q  | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 316 |fsgnjn.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 317 |fsgnjx.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 318 |fcvt.s.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 319 |fcvt.q.s | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 320 |fcvt.d.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 321 |fcvt.q.d | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 322 |fcvt.w.q | rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 323 |fcvt.wu.q| rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 324 |fcvt.q.w | frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 325 |fcvt.q.wu| frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 326
 327 # RV64Q    "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
 328
 329 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 330 | -------- | -------- | ------- | ------- |  |
 331 |fcvt.l.q | rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 332 |fcvt.lu.q| rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 333 |fcvt.q.l | frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 334 |fcvt.q.lu| frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 335
 336 # RV128Q   "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
 337
 338 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 339 | -------- | -------- | ------- | ------- |  |
 340 |fmv.x.q  | rd frs1  | r+rf          | rv64q rv128q | 2v  |
 341 |fmv.q.x  | frd rs1  | r+fr          | rv64q rv128q | 2v  |
 342
 343 # RV32C/RV64C/RV128C    "RV32C/RV64C/RV128C Standard Extension for Compressed Instructions"
 344
 345 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 346 | -------- | -------- | ------- | ------- |  |
 347 |c.addi4spn|crdq       cimm4spn  | ciw·4spn  | rv32c rv64c | - |
 348 |c.nop    |                      | ci·none   | rv32c rv64c | - |
 349 |c.jal    |               cimmj  | cj·jal    | rv32c       | - |
 350 |c.j      |               cimmj  | cj        | rv32c rv64c | - |
 351 |c.jr     | crd0 crs1            | cr·jr     | rv32c rv64c | - |
 352 |c.ebreak |                      | ci·none   | rv32c rv64c | - |
 353 |c.jalr   | crd0 crs1            | cr·jalr   | rv32c rv64c | - |
 354 |c.mv     | crd crs2             | cr·mv     | rv32c rv64c | 2v  |
 355 |c.fld    | cfrdq crs1q   cimmd  | cl·ld+f   | rv32c rv64c | vld  |
 356 |c.lw     | crdq  crs1q   cimmw  | cl·lw     | rv32c rv64c | vld  |
 357 |c.flw    | cfrdq crs1q   cimmw  | cl·lw+f   | rv32c       | vld  |
 358 |c.ld     | crdq  crs1q   cimmd  | cl·ld           | rv64c | vld  |
 359 |c.lq     | crdq crs1q    cimmq  | cl·lq           | rv128c | vld  |
 360 |c.fsd    | crs1q cfrs2q  cimmd  | cs·sd+f   | rv32c rv64c | vst  |
 361 |c.sw     | crs1q crs2q   cimmw  | cs·sw     | rv32c rv64c | vst  |
 362 |c.fsw    | crs1q cfrs2q  cimmw  | cs·sw+f   | rv32c       | vst  |
 363 |c.sd     | crs1q crs2q   cimmd  | cs·sd           | rv64c | vst  |
 364 |c.sq     | crs1q crs2q   cimmq  | cs·sq           | rv128c | vst  |
 365 |c.addi16sp|crs1rd     cimm16sp  | ci·16sp   | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) |
 366 |c.addi   | crs1rd      cnzimmi  | ci        | rv32c rv64c | sv  |
 367 |c.li     | crs1rd        cimmi  | ci·li     | rv32c rv64c | sv  |
 368 |c.lui    | crd          cimmui  | ci·lui    | rv32c rv64c | sv |
 369 |c.srli   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 370 |c.srai   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 371 |c.slli   | crs1rd      cimmsh5  | ci·sh5    | rv32c       | sv  |
 372 |c.andi   | crs1rdq     cnzimmi  | cb·imm    | rv32c rv64c | sv  |
 373 |c.sub    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 374 |c.xor    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 375 |c.or     | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 376 |c.and    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 377 |c.subw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 378 |c.addw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 379 |c.add    | crs1rd crs2          | cr        | rv32c rv64c | sv  |
 380 |c.addiw  | crs1rd        cimmi  | ci              | rv64c | sv  |
 381 |c.srli   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 382 |c.srai   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 383 |c.slli   | crs1rd      cimmsh6  | ci·sh6          | rv64c | sv  |
 384 |c.beqz   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 385 |c.bnez   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 386 |c.fldsp  | cfrd       cimmldsp  | ci·ldsp+f | rv32c rv64c | VLU  |
 387 |c.lwsp   | crd        cimmlwsp  | ci·lwsp   | rv32c rv64c | VLU  |
 388 |c.flwsp  | cfrd       cimmlwsp  | ci·lwsp+f | rv32c       | VLU  |
 389 |c.ldsp   | crd        cimmldsp  | ci·ldsp         | rv64c | VLU  |
 390 |c.lqsp   | crd        cimmlqsp  | ci·lqsp         | rv128c | VLU  |
 391 |c.fsdsp  | cfrs2      cimmsdsp  | css·sdsp+f | rv32c rv64c | VSU  |
 392 |c.swsp   | crs2       cimmswsp  | css·swsp  | rv32c rv64c | VSU  |
 393 |c.fswsp  | cfrs2      cimmswsp  | css·swsp+f | rv32c      | VSU  |
 394 |c.sdsp   | crs2       cimmsdsp  | css·sdsp        | rv64c | VSU  |
 395 |c.sqsp   | crs2       cimmsqsp  | css·sqsp        | rv128c | VSU  |