simple_v_extension/opcodes.mdwn

   1
   2 # RV32I    "RV32I Base Integer Instruction Set"
   3
   4 | (23..18) | (17..12) | (11..6) | (5...0) |
   5 | -------- | -------- | ------- | ------- |
   6 |lui      | rd imm20        | u     | rv32i rv64i rv128i |   |
   7 |auipc    | rd oimm20       | u+o  | rv32i rv64i rv128i |   |
   8 |jal      | rd jimm20       | uj   | rv32i rv64i rv128i |   |
   9 |jalr     | rd rs1 oimm12   | i+o  | rv32i rv64i rv128i |   |
  10 |beq      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  11 |bne      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  12 |blt      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  13 |bge      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  14 |bltu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  15 |bgeu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i |   |
  16 |lb       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i |   |
  17 |lh       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i |   |
  18 |lw       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i |   |
  19 |lbu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i |   |
  20 |lhu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i |   |
  21 |sb       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i |   |
  22 |sh       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i |   |
  23 |sw       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i |   |
  24 |addi     | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  25 |slti     | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  26 |sltiu    | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  27 |xori     | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  28 |ori      | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  29 |andi     | rd rs1 imm12    | i    | rv32i rv64i rv128i |   |
  30 |slli     | rd rs1 shamt5   | i·sh5             | rv32i |   |
  31 |srli     | rd rs1 shamt5   | i·sh5             | rv32i |   |
  32 |srai     | rd rs1 shamt5   | i·sh5             | rv32i |   |
  33 |add      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  34 |sub      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  35 |sll      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  36 |slt      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  37 |sltu     | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  38 |xor      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  39 |srl      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  40 |sra      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  41 |or       | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  42 |and      | rd rs1 rs2      | r    | rv32i rv64i rv128i |   |
  43 |fence    |                 | r·f | rv32i rv64i rv128i |   |
  44 |fence.i  |                 | none | rv32i rv64i rv128i |   |
  45
  46 # RV64I    "RV64I Base Integer Instruction Set (in addition to RV32I)"
  47
  48 | (23..18) | (17..12) | (11..6) | (5...0) |
  49 | -------- | -------- | ------- | ------- |
  50 |lwu      | rd rs1 oimm12   |  i+l        | rv64i rv128i |   |
  51 |ld       | rd rs1 oimm12   |  i+l        | rv64i rv128i |   |
  52 |sd       | rs1 rs2 simm12  |  s          | rv64i rv128i |   |
  53 |slli     | rd rs1 shamt6   |  i·sh6             | rv64i |   |
  54 |srli     | rd rs1 shamt6   |  i·sh6             | rv64i |   |
  55 |srai     | rd rs1 shamt6   |  i·sh6             | rv64i |   |
  56 |addiw    | rd rs1 imm12    |  i          | rv64i rv128i |   |
  57 |slliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i |   |
  58 |srliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i |   |
  59 |sraiw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i |   |
  60 |addw     | rd rs1 rs2      |  r          | rv64i rv128i |   |
  61 |subw     | rd rs1 rs2      |  r          | rv64i rv128i |   |
  62 |sllw     | rd rs1 rs2      |  r          | rv64i rv128i |   |
  63 |srlw     | rd rs1 rs2      |  r          | rv64i rv128i |   |
  64 |sraw     | rd rs1 rs2      |  r          | rv64i rv128i |   |
  65
  66 # RV128I   "RV128I Base Integer Instruction Set (in addition to RV64I)"
  67
  68 | (23..18) | (17..12) | (11..6) | (5...0) |
  69 | -------- | -------- | ------- | ------- |
  70 |ldu      | rd rs1 oimm12  |   i+l              | rv128i |   |
  71 |lq       | rd rs1 oimm12  |   i+l              | rv128i |   |
  72 |sq       | rs1 rs2 simm12 |   s                | rv128i |   |
  73 |slli     | rd rs1 shamt7  |   i·sh7            | rv128i |   |
  74 |srli     | rd rs1 shamt7  |   i·sh7            | rv128i |   |
  75 |srai     | rd rs1 shamt7  |   i·sh7            | rv128i |   |
  76 |addid    | rd rs1 imm12   |   i                | rv128i |   |
  77 |sllid    | rd rs1 shamt6  |   i·sh6            | rv128i |   |
  78 |srlid    | rd rs1 shamt6  |   i·sh6            | rv128i |   |
  79 |sraid    | rd rs1 shamt6  |   i·sh6            | rv128i |   |
  80 |addd     | rd rs1 rs2     |   r                | rv128i |   |
  81 |subd     | rd rs1 rs2     |   r                | rv128i |   |
  82 |slld     | rd rs1 rs2     |   r                | rv128i |   |
  83 |srld     | rd rs1 rs2     |   r                | rv128i |   |
  84 |srad     | rd rs1 rs2     |   r                | rv128i |   |
  85
  86 # RV32M    "RV32M Standard Extension for Integer Multiply and Divide"
  87
  88 | (23..18) | (17..12) | (11..6) | (5...0) |
  89 | -------- | -------- | ------- | ------- |
  90 |mul      | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  91 |mulh     | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  92 |mulhsu   | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  93 |mulhu    | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  94 |div      | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  95 |divu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  96 |rem      | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  97 |remu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
  98
  99 # RV64M    "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
 100
 101 | (23..18) | (17..12) | (11..6) | (5...0) |
 102 | -------- | -------- | ------- | ------- |
 103 |mulw     | rd rs1 rs2   |     r          | rv64m rv128m |   |
 104 |divw     | rd rs1 rs2   |     r          | rv64m rv128m |   |
 105 |divuw    | rd rs1 rs2   |     r          | rv64m rv128m |   |
 106 |remw     | rd rs1 rs2   |     r          | rv64m rv128m |   |
 107 |remuw    | rd rs1 rs2   |     r          | rv64m rv128m |   |
 108
 109 # RV128M   "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
 110
 111 | (23..18) | (17..12) | (11..6) | (5...0) |
 112 | -------- | -------- | ------- | ------- |
 113 |muld     | rd rs1 rs2   |     r                | rv128m |   |
 114 |divd     | rd rs1 rs2   |     r                | rv128m |   |
 115 |divud    | rd rs1 rs2   |     r                | rv128m |   |
 116 |remd     | rd rs1 rs2   |     r                | rv128m |   |
 117 |remud    | rd rs1 rs2   |     r                | rv128m |   |
 118
 119 # RV32A    "RV32A Standard Extension for Atomic Instructions"
 120
 121 | (23..18) | (17..12) | (11..6) | (5...0) |
 122 | -------- | -------- | ------- | ------- |
 123 |lr.w     | rd rs1          | r·l | rv32a rv64a rv128a |   |
 124 |sc.w     | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 125 |amoswap.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 126 |amoadd.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 127 |amoxor.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 128 |amoor.w  | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 129 |amoand.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 130 |amomin.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 131 |amomax.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 132 |amominu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 133 |amomaxu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 134
 135 # RV64A    "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
 136
 137 | (23..18) | (17..12) | (11..6) | (5...0) |
 138 | -------- | -------- | ------- | ------- |
 139 |lr.d     | rd rs1          | r·l      | rv64a rv128a |   |
 140 |sc.d     | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 141 |amoswap.d| rd rs1 rs2      | r·a      | rv64a rv128a |   |
 142 |amoadd.d | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 143 |amoxor.d | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 144 |amoor.d  | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 145 |amoand.d | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 146 |amomin.d | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 147 |amomax.d | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 148 |amominu.d| rd rs1 rs2      | r·a      | rv64a rv128a |   |
 149 |amomaxu.d| rd rs1 rs2      | r·a      | rv64a rv128a |   |
 150
 151 # RV128A   "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
 152
 153 | (23..18) | (17..12) | (11..6) | (5...0) |
 154 | -------- | -------- | ------- | ------- |
 155 |lr.q     | rd rs1          | r·l | rv128a |   |
 156 |sc.q     | rd rs1 rs2      | r·a | rv128a |   |
 157 |amoswap.q| rd rs1 rs2      | r·a | rv128a |   |
 158 |amoadd.q | rd rs1 rs2      | r·a | rv128a |   |
 159 |amoxor.q | rd rs1 rs2      | r·a | rv128a |   |
 160 |amoor.q  | rd rs1 rs2      | r·a | rv128a |   |
 161 |amoand.q | rd rs1 rs2      | r·a | rv128a |   |
 162 |amomin.q | rd rs1 rs2      | r·a | rv128a |   |
 163 |amomax.q | rd rs1 rs2      | r·a | rv128a |   |
 164 |amominu.q| rd rs1 rs2      | r·a | rv128a |   |
 165 |amomaxu.q| rd rs1 rs2      | r·a | rv128a |   |
 166
 167 # RV32S    "RV32S Standard Extension for Supervisor-level Instructions"
 168
 169 | (23..18) | (17..12) | (11..6) | (5...0) |
 170 | -------- | -------- | ------- | ------- |
 171 |ecall     |                         | none    | rv32s rv64s rv128s |   |
 172 |ebreak    |                         | none    | rv32s rv64s rv128s |   |
 173 |uret      |                         | none    | rv32s rv64s rv128s |   |
 174 |sret      |                         | none    | rv32s rv64s rv128s |   |
 175 |hret      |                         | none    | rv32s rv64s rv128s |   |
 176 |mret      |                         | none    | rv32s rv64s rv128s |   |
 177 |dret      |                         | none    | rv32s rv64s rv128s |   |
 178 |sfence.vm |         rs1             | r+sf    | rv32s rv64s rv128s |   |
 179 |sfence.vma| rs1 rs2                 | r+sfa   | rv32s rv64s rv128s |   |
 180 |wfi       |                         | none    | rv32s rv64s rv128s |   |
 181 |csrrw     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s |   |
 182 |csrrs     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s |   |
 183 |csrrc     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s |   |
 184 |csrrwi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s |   |
 185 |csrrsi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s |   |
 186 |csrrci    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s |   |
 187
 188 # RV32F    "RV32F Standard Extension for Single-Precision Floating-Point"
 189
 190 | (23..18) | (17..12) | (11..6) | (5...0) |
 191 | -------- | -------- | ------- | ------- | |
 192 |flw      | frd rs1           oimm12      | i+lf  | rv32f rv64f rv128f |   |
 193 |fsw      | rs1 frs2          simm12      | s+f   | rv32f rv64f rv128f |   |
 194 |fmadd.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f |   |
 195 |fmsub.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f |   |
 196 |fnmsub.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f |   |
 197 |fnmadd.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f |   |
 198 |fadd.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f |   |
 199 |fsub.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f |   |
 200 |fmul.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f |   |
 201 |fdiv.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f |   |
 202 |fsgnj.s  | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f |   |
 203 |fsgnjn.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f |   |
 204 |fsgnjx.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f |   |
 205 |fmin.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f |   |
 206 |fmax.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f |   |
 207 |fsqrt.s  | frd frs1                   rm | r·m+ff | rv32f rv64f rv128f |   |
 208 |fle.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f |   |
 209 |flt.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f |   |
 210 |feq.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f |   |
 211 |fcvt.w.s | rd frs1                    rm | r·m+rf | rv32f rv64f rv128f |   |
 212 |fcvt.wu.s| rd frs1                    rm | r·m+rf | rv32f rv64f rv128f |   |
 213 |fcvt.s.w | frd rs1                    rm | r·m+fr | rv32f rv64f rv128f |   |
 214 |fcvt.s.wu| frd rs1                    rm | r·m+fr | rv32f rv64f rv128f |   |
 215 |fmv.x.s  | rd frs1                       | r+rf  | rv32f rv64f rv128f |   |
 216 |fclass.s | rd frs1                       | r+rf  | rv32f rv64f rv128f |   |
 217 |fmv.s.x  | frd rs1                       | r+fr  | rv32f rv64f rv128f |   |
 218
 219 # RV64F    "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
 220
 221 | (23..18) | (17..12) | (11..6) | (5...0) |
 222 | -------- | -------- | ------- | ------- |
 223 |fcvt.l.s | rd frs1  rm  |     r·m+rf      | rv64f rv128f |   |
 224 |fcvt.lu.s| rd frs1  rm  |     r·m+rf      | rv64f rv128f |   |
 225 |fcvt.s.l | frd rs1  rm  |     r·m+fr      | rv64f rv128f |   |
 226 |fcvt.s.lu| frd rs1  rm  |     r·m+fr      | rv64f rv128f |   |
 227
 228 # RV32D    "RV32D Standard Extension for Double-Precision Floating-Point"
 229
 230 | (23..18) | (17..12) | (11..6) | (5...0) |
 231 | -------- | -------- | ------- | ------- |
 232 |fld      | frd rs1   oimm12      | i+lf  | rv32d rv64d rv128d |   |
 233 |fsd      | rs1 frs2  simm12      | s+f   | rv32d rv64d rv128d |   |
 234 |fmadd.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d |   |
 235 |fmsub.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d |   |
 236 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d |   |
 237 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d |   |
 238 |fadd.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d |   |
 239 |fsub.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d |   |
 240 |fmul.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d |   |
 241 |fdiv.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d |   |
 242 |fsgnj.d  | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d |   |
 243 |fsgnjn.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d |   |
 244 |fsgnjx.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d |   |
 245 |fmin.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d |   |
 246 |fmax.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d |   |
 247 |fcvt.s.d | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d |   |
 248 |fcvt.d.s | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d |   |
 249 |fsqrt.d  | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d |   |
 250 |fle.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d |   |
 251 |flt.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d |   |
 252 |feq.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d |   |
 253 |fcvt.w.d | rd frs1  rm           | r·m+rf | rv32d rv64d rv128d |   |
 254 |fcvt.wu.d| rd frs1  rm           | r·m+rf | rv32d rv64d rv128d |   |
 255 |fcvt.d.w | frd rs1  rm           | r·m+fr | rv32d rv64d rv128d |   |
 256 |fcvt.d.wu| frd rs1  rm           | r·m+fr | rv32d rv64d rv128d |   |
 257 |fclass.d | rd frs1               | r+rf  | rv32d rv64d rv128d |   |
 258
 259 # RV64D    "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
 260
 261 | (23..18) | (17..12) | (11..6) | (5...0) |
 262 | -------- | -------- | ------- | ------- |
 263 |fcvt.l.d | rd frs1  rm      | r·m+rf      | rv64d rv128d |   |
 264 |fcvt.lu.d| rd frs1  rm      | r·m+rf      | rv64d rv128d |   |
 265 |fmv.x.d  | rd frs1          | r+rf        | rv64d rv128d |   |
 266 |fcvt.d.l | frd rs1  rm      | r·m+fr      | rv64d rv128d |   |
 267 |fcvt.d.lu| frd rs1  rm      | r·m+fr      | rv64d rv128d |   |
 268 |fmv.d.x  | frd rs1          | r+fr        | rv64d rv128d |   |
 269
 270 # RV32Q    "RV32Q Standard Extension for Quad-Precision Floating-Point"
 271
 272 | (23..18) | (17..12) | (11..6) | (5...0) |
 273 | -------- | -------- | ------- | ------- |
 274 |flq      | frd rs1       oimm12  | i+lf   | rv32q rv64q rv128q |   |
 275 |fsq      | rs1 frs2      simm12  | s+f    | rv32q rv64q rv128q |   |
 276 |fmadd.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q |   |
 277 |fmsub.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q |   |
 278 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q |   |
 279 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q |   |
 280 |fadd.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q |   |
 281 |fsub.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q |   |
 282 |fmul.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q |   |
 283 |fdiv.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q |   |
 284 |fsgnj.q  | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q |   |
 285 |fsgnjn.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q |   |
 286 |fsgnjx.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q |   |
 287 |fmin.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q |   |
 288 |fmax.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q |   |
 289 |fcvt.s.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q |   |
 290 |fcvt.q.s | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q |   |
 291 |fcvt.d.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q |   |
 292 |fcvt.q.d | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q |   |
 293 |fsqrt.q  | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q |   |
 294 |fle.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q |   |
 295 |flt.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q |   |
 296 |feq.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q |   |
 297 |fcvt.w.q | rd frs1  rm           | r·m+rf | rv32q rv64q rv128q |   |
 298 |fcvt.wu.q| rd frs1  rm           | r·m+rf | rv32q rv64q rv128q |   |
 299 |fcvt.q.w | frd rs1  rm           | r·m+fr | rv32q rv64q rv128q |   |
 300 |fcvt.q.wu| frd rs1  rm           | r·m+fr | rv32q rv64q rv128q |   |
 301 |fclass.q | rd frs1               | r+rf   | rv32q rv64q rv128q |   |
 302
 303 # RV64Q    "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
 304
 305 | (23..18) | (17..12) | (11..6) | (5...0) |
 306 | -------- | -------- | ------- | ------- |
 307 |fcvt.l.q | rd frs1  rm       | r·m+rf        | rv64q rv128q |   |
 308 |fcvt.lu.q| rd frs1  rm       | r·m+rf        | rv64q rv128q |   |
 309 |fcvt.q.l | frd rs1  rm       | r·m+fr        | rv64q rv128q |   |
 310 |fcvt.q.lu| frd rs1  rm       | r·m+fr        | rv64q rv128q |   |
 311
 312 # RV128Q   "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
 313
 314 | (23..18) | (17..12) | (11..6) | (5...0) |
 315 | -------- | -------- | ------- | ------- |
 316 |fmv.x.q  | rd frs1  | r+rf          | rv64q rv128q |   |
 317 |fmv.q.x  | frd rs1  | r+fr          | rv64q rv128q |   |
 318
 319 # RV32C    "RV32C Standard Extension for Compressed Instructions"
 320
 321 | (23..18) | (17..12) | (11..6) | (5...0) |
 322 | -------- | -------- | ------- | ------- |
 323 |c.addi4spn|crdq       cimm4spn  | ciw·4spn  | rv32c rv64c |   |
 324 |c.fld    | cfrdq crs1q   cimmd  | cl·ld+f   | rv32c rv64c |   |
 325 |c.lw     | crdq  crs1q   cimmw  | cl·lw     | rv32c rv64c |   |
 326 |c.flw    | cfrdq crs1q   cimmw  | cl·lw+f   | rv32c |   |
 327 |c.fsd    | crs1q cfrs2q  cimmd  | cs·sd+f   | rv32c rv64c |   |
 328 |c.sw     | crs1q crs2q   cimmw  | cs·sw     | rv32c rv64c |   |
 329 |c.fsw    | crs1q cfrs2q  cimmw  | cs·sw+f   | rv32c |   |
 330 |c.nop    |                      | ci·none   | rv32c rv64c |   |
 331 |c.addi   | crs1rd      cnzimmi  | ci        | rv32c rv64c |   |
 332 |c.jal    |               cimmj  | cj·jal    | rv32c |   |
 333 |c.li     | crs1rd        cimmi  | ci·li     | rv32c rv64c |   |
 334 |c.addi16sp|crs1rd     cimm16sp  | ci·16sp   | rv32c rv64c |   |
 335 |c.lui    | crd          cimmui  | ci·lui    | rv32c rv64c |   |
 336 |c.srli   | crs1rdq     cimmsh5  | cb·sh5    | rv32c |   |
 337 |c.srai   | crs1rdq     cimmsh5  | cb·sh5    | rv32c |   |
 338 |c.andi   | crs1rdq     cnzimmi  | cb·imm    | rv32c rv64c |   |
 339 |c.sub    | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 340 |c.xor    | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 341 |c.or     | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 342 |c.and    | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 343 |c.subw   | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 344 |c.addw   | crs1rdq crs2q        | cs        | rv32c rv64c |   |
 345 |c.j      |               cimmj  | cj        | rv32c rv64c |   |
 346 |c.beqz   | crs1q         cimmb  | cb        | rv32c rv64c |   |
 347 |c.bnez   | crs1q         cimmb  | cb        | rv32c rv64c |   |
 348 |c.slli   | crs1rd      cimmsh5  | ci·sh5    | rv32c |   |
 349 |c.fldsp  | cfrd       cimmldsp  | ci·ldsp+f | rv32c rv64c |   |
 350 |c.lwsp   | crd        cimmlwsp  | ci·lwsp   | rv32c rv64c |   |
 351 |c.flwsp  | cfrd       cimmlwsp  | ci·lwsp+f | rv32c |   |
 352 |c.jr     | crd0 crs1            | cr·jr     | rv32c rv64c |   |
 353 |c.mv     | crd crs2             | cr·mv     | rv32c rv64c |   |
 354 |c.ebreak |                      | ci·none   | rv32c rv64c |   |
 355 |c.jalr   | crd0 crs1            | cr·jalr   | rv32c rv64c |   |
 356 |c.add    | crs1rd crs2          | cr        | rv32c rv64c |   |
 357 |c.fsdsp  | cfrs2      cimmsdsp  | css·sdsp+f | rv32c rv64c |   |
 358 |c.swsp   | crs2       cimmswsp  | css·swsp  | rv32c rv64c |   |
 359 |c.fswsp  | cfrs2      cimmswsp  | css·swsp+f | rv32c |   |
 360
 361 # RV64C    "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)"
 362
 363 | (23..18) | (17..12) | (11..6) | (5...0) |
 364 | -------- | -------- | ------- | ------- |
 365 |c.ld     | crdq  crs1q   cimmd  | cl·ld           | rv64c |   |
 366 |c.sd     | crs1q crs2q   cimmd  | cs·sd           | rv64c |   |
 367 |c.addiw  | crs1rd        cimmi  | ci              | rv64c |   |
 368 |c.srli   | crs1rdq     cimmsh6  | cb·sh6          | rv64c |   |
 369 |c.srai   | crs1rdq     cimmsh6  | cb·sh6          | rv64c |   |
 370 |c.slli   | crs1rd      cimmsh6  | ci·sh6          | rv64c |   |
 371 |c.ldsp   | crd        cimmldsp  | ci·ldsp         | rv64c |   |
 372 |c.sdsp   | crs2       cimmsdsp  | css·sdsp        | rv64c |   |
 373
 374 # RV128C   "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)"
 375
 376 | (23..18) | (17..12) | (11..6) | (5...0) |
 377 | -------- | -------- | ------- | ------- |
 378 |c.lq     | crdq crs1q    cimmq  | cl·lq           | rv128c |   |
 379 |c.sq     | crs1q crs2q   cimmq  | cs·sq           | rv128c |   |
 380 |c.lqsp   | crd        cimmlqsp  | ci·lqsp         | rv128c |   |
 381 |c.sqsp   | crs2       cimmsqsp  | css·sqsp        | rv128c |   |