simple_v_extension/opcodes.mdwn

   1
   2 # RV32I/RV64I/RV128I    "RV32I/RV64I/RV128I Base Integer Instruction Set"
   3
   4 | (23..18) | (17..12) | (11..6) | (5...0) |  |
   5 | -------- | -------- | ------- | ------- |  |
   6 |auipc    | rd oimm20       | u+o  | rv32i rv64i rv128i | -  |
   7 |jal      | rd jimm20       | uj   | rv32i rv64i rv128i | -  |
   8 |jalr     | rd rs1 oimm12   | i+o  | rv32i rv64i rv128i | -  |
   9 |fence    |                 | r·f | rv32i rv64i rv128i | -  |
  10 |fence.i  |                 | none | rv32i rv64i rv128i | -  |
  11 |lui      | rd imm20        | u     | rv32i rv64i rv128i | sv  |
  12 |beq      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  13 |bne      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  14 |blt      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  15 |bge      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  16 |bltu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  17 |bgeu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  18 |lb       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vls  |
  19 |lh       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vls  |
  20 |lw       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vls  |
  21 |lbu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vls  |
  22 |lhu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vls  |
  23 |sb       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vls  |
  24 |sh       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vls  |
  25 |sw       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vls  |
  26 |lwu      | rd rs1 oimm12   |  i+l        | rv64i rv128i | vls  |
  27 |ld       | rd rs1 oimm12   |  i+l        | rv64i rv128i | vls  |
  28 |sd       | rs1 rs2 simm12  |  s          | rv64i rv128i | vls  |
  29 |ldu      | rd rs1 oimm12  |   i+l              | rv128i | vls  |
  30 |lq       | rd rs1 oimm12  |   i+l              | rv128i | vls  |
  31 |sq       | rs1 rs2 simm12 |   s                | rv128i | vls  |
  32 |addi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  33 |slti     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  34 |sltiu    | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  35 |xori     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  36 |ori      | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  37 |andi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  38 |slli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  39 |srli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  40 |srai     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  41 |add      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  42 |sub      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  43 |sll      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  44 |slt      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  45 |sltu     | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  46 |xor      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  47 |srl      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  48 |sra      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  49 |or       | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  50 |and      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  51 |slli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  52 |srli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  53 |srai     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
  54 |addiw    | rd rs1 imm12    |  i          | rv64i rv128i | sv  |
  55 |slliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  56 |srliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  57 |sraiw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
  58 |addw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  59 |subw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  60 |sllw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  61 |srlw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  62 |sraw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
  63 |slli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
  64 |srli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
  65 |srai     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
  66 |addid    | rd rs1 imm12   |   i                | rv128i | sv  |
  67 |sllid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
  68 |srlid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
  69 |sraid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
  70 |addd     | rd rs1 rs2     |   r                | rv128i | sv  |
  71 |subd     | rd rs1 rs2     |   r                | rv128i | sv  |
  72 |slld     | rd rs1 rs2     |   r                | rv128i | sv  |
  73 |srld     | rd rs1 rs2     |   r                | rv128i | sv  |
  74 |srad     | rd rs1 rs2     |   r                | rv128i | sv  |
  75
  76 # RV32M    "RV32M Standard Extension for Integer Multiply and Divide"
  77
  78 | (23..18) | (17..12) | (11..6) | (5...0) |  |
  79 | -------- | -------- | ------- | ------- |  |
  80 |mul      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  81 |mulh     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  82 |mulhsu   | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  83 |mulhu    | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  84 |div      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  85 |divu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  86 |rem      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  87 |remu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
  88
  89 # RV64M    "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
  90
  91 | (23..18) | (17..12) | (11..6) | (5...0) |  |
  92 | -------- | -------- | ------- | ------- |  |
  93 |mulw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
  94 |divw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
  95 |divuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
  96 |remw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
  97 |remuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
  98
  99 # RV128M   "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
 100
 101 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 102 | -------- | -------- | ------- | ------- |  |
 103 |muld     | rd rs1 rs2   |     r                | rv128m | sv  |
 104 |divd     | rd rs1 rs2   |     r                | rv128m | sv  |
 105 |divud    | rd rs1 rs2   |     r                | rv128m | sv  |
 106 |remd     | rd rs1 rs2   |     r                | rv128m | sv  |
 107 |remud    | rd rs1 rs2   |     r                | rv128m | sv  |
 108
 109 # RV32A    "RV32A Standard Extension for Atomic Instructions"
 110
 111 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 112 | -------- | -------- | ------- | ------- |  |
 113 |lr.w     | rd rs1          | r·l | rv32a rv64a rv128a | -  |
 114 |sc.w     | rd rs1 rs2      | r·a | rv32a rv64a rv128a | -  |
 115 |amoswap.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 116 |amoadd.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 117 |amoxor.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 118 |amoor.w  | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 119 |amoand.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 120 |amomin.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 121 |amomax.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 122 |amominu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 123 |amomaxu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 124
 125 # RV64A    "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
 126
 127 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 128 | -------- | -------- | ------- | ------- |  |
 129 |lr.d     | rd rs1          | r·l      | rv64a rv128a | - |
 130 |sc.d     | rd rs1 rs2      | r·a      | rv64a rv128a | - |
 131 |amoswap.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 132 |amoadd.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 133 |amoxor.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 134 |amoor.d  | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 135 |amoand.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 136 |amomin.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 137 |amomax.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 138 |amominu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 139 |amomaxu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 140
 141 # RV128A   "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
 142
 143 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 144 | -------- | -------- | ------- | ------- |  |
 145 |lr.q     | rd rs1          | r·l | rv128a | - |
 146 |sc.q     | rd rs1 rs2      | r·a | rv128a | - |
 147 |amoswap.q| rd rs1 rs2      | r·a | rv128a | sv  |
 148 |amoadd.q | rd rs1 rs2      | r·a | rv128a | sv  |
 149 |amoxor.q | rd rs1 rs2      | r·a | rv128a | sv  |
 150 |amoor.q  | rd rs1 rs2      | r·a | rv128a | sv  |
 151 |amoand.q | rd rs1 rs2      | r·a | rv128a | sv  |
 152 |amomin.q | rd rs1 rs2      | r·a | rv128a | sv  |
 153 |amomax.q | rd rs1 rs2      | r·a | rv128a | sv  |
 154 |amominu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 155 |amomaxu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 156
 157 # RV32S    "RV32S Standard Extension for Supervisor-level Instructions"
 158
 159 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 160 | -------- | -------- | ------- | ------- |  |
 161 |ecall     |                         | none    | rv32s rv64s rv128s | - |
 162 |ebreak    |                         | none    | rv32s rv64s rv128s | - |
 163 |uret      |                         | none    | rv32s rv64s rv128s | - |
 164 |sret      |                         | none    | rv32s rv64s rv128s | - |
 165 |hret      |                         | none    | rv32s rv64s rv128s | - |
 166 |mret      |                         | none    | rv32s rv64s rv128s | - |
 167 |dret      |                         | none    | rv32s rv64s rv128s | - |
 168 |sfence.vm |         rs1             | r+sf    | rv32s rv64s rv128s | - |
 169 |sfence.vma| rs1 rs2                 | r+sfa   | rv32s rv64s rv128s | - |
 170 |wfi       |                         | none    | rv32s rv64s rv128s | - |
 171 |csrrw     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 172 |csrrs     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 173 |csrrc     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 174 |csrrwi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 175 |csrrsi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 176 |csrrci    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 177
 178 # RV32F    "RV32F Standard Extension for Single-Precision Floating-Point"
 179
 180 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 181 | -------- | -------- | ------- | ------- | |
 182 |flw      | frd rs1           oimm12      | i+lf  | rv32f rv64f rv128f | vld  |
 183 |fsw      | rs1 frs2          simm12      | s+f   | rv32f rv64f rv128f | vld  |
 184 |fmadd.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 185 |fmsub.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 186 |fnmsub.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 187 |fnmadd.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 188 |fadd.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 189 |fsub.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 190 |fmul.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 191 |fdiv.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 192 |fsgnj.s  | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 193 |fsgnjn.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 194 |fsgnjx.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 195 |fmin.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 196 |fmax.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 197 |fsqrt.s  | frd frs1                   rm | r·m+ff | rv32f rv64f rv128f | sv  |
 198 |fle.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 199 |flt.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 200 |feq.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 201 |fcvt.w.s | rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 202 |fcvt.wu.s| rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 203 |fcvt.s.w | frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 204 |fcvt.s.wu| frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 205 |fmv.x.s  | rd frs1                       | r+rf  | rv32f rv64f rv128f | 2v  |
 206 |fclass.s | rd frs1                       | r+rf  | rv32f rv64f rv128f | sv  |
 207 |fmv.s.x  | frd rs1                       | r+fr  | rv32f rv64f rv128f | 2v  |
 208
 209 # RV64F    "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
 210
 211 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 212 | -------- | -------- | ------- | ------- |  |
 213 |fcvt.l.s | rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 214 |fcvt.lu.s| rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 215 |fcvt.s.l | frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 216 |fcvt.s.lu| frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 217
 218 # RV32D    "RV32D Standard Extension for Double-Precision Floating-Point"
 219
 220 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 221 | -------- | -------- | ------- | ------- |  |
 222 |fld      | frd rs1   oimm12      | i+lf  | rv32d rv64d rv128d | vld  |
 223 |fsd      | rs1 frs2  simm12      | s+f   | rv32d rv64d rv128d | vld  |
 224 |fmadd.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 225 |fmsub.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 226 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 227 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 228 |fadd.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 229 |fsub.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 230 |fmul.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 231 |fdiv.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 232 |fsgnj.d  | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 233 |fsgnjn.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 234 |fsgnjx.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 235 |fmin.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 236 |fmax.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 237 |fcvt.s.d | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 238 |fcvt.d.s | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 239 |fsqrt.d  | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | sv  |
 240 |fle.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 241 |flt.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 242 |feq.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 243 |fcvt.w.d | rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 244 |fcvt.wu.d| rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 245 |fcvt.d.w | frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 246 |fcvt.d.wu| frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 247 |fclass.d | rd frs1               | r+rf  | rv32d rv64d rv128d | sv  |
 248
 249 # RV64D    "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
 250
 251 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 252 | -------- | -------- | ------- | ------- |  |
 253 |fcvt.l.d | rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 254 |fcvt.lu.d| rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 255 |fmv.x.d  | rd frs1          | r+rf        | rv64d rv128d | 2v  |
 256 |fcvt.d.l | frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 257 |fcvt.d.lu| frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 258 |fmv.d.x  | frd rs1          | r+fr        | rv64d rv128d | 2v  |
 259
 260 # RV32Q    "RV32Q Standard Extension for Quad-Precision Floating-Point"
 261
 262 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 263 | -------- | -------- | ------- | ------- |  |
 264 |flq      | frd rs1       oimm12  | i+lf   | rv32q rv64q rv128q | vls  |
 265 |fsq      | rs1 frs2      simm12  | s+f    | rv32q rv64q rv128q | vls  |
 266 |fmadd.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 267 |fmsub.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 268 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 269 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 270 |fadd.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 271 |fsub.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 272 |fmul.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 273 |fdiv.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 274 |fsgnj.q  | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 275 |fsgnjn.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 276 |fsgnjx.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 277 |fmin.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 278 |fmax.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 279 |fcvt.s.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 280 |fcvt.q.s | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 281 |fcvt.d.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 282 |fcvt.q.d | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 283 |fsqrt.q  | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | sv  |
 284 |fle.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 285 |flt.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 286 |feq.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 287 |fcvt.w.q | rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 288 |fcvt.wu.q| rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 289 |fcvt.q.w | frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 290 |fcvt.q.wu| frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 291 |fclass.q | rd frs1               | r+rf   | rv32q rv64q rv128q | sv  |
 292
 293 # RV64Q    "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
 294
 295 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 296 | -------- | -------- | ------- | ------- |  |
 297 |fcvt.l.q | rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 298 |fcvt.lu.q| rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 299 |fcvt.q.l | frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 300 |fcvt.q.lu| frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 301
 302 # RV128Q   "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
 303
 304 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 305 | -------- | -------- | ------- | ------- |  |
 306 |fmv.x.q  | rd frs1  | r+rf          | rv64q rv128q | 2v  |
 307 |fmv.q.x  | frd rs1  | r+fr          | rv64q rv128q | 2v  |
 308
 309 # RV32C    "RV32C Standard Extension for Compressed Instructions"
 310
 311 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 312 | -------- | -------- | ------- | ------- |  |
 313 |c.addi4spn|crdq       cimm4spn  | ciw·4spn  | rv32c rv64c | - |
 314 |c.fld    | cfrdq crs1q   cimmd  | cl·ld+f   | rv32c rv64c | vls  |
 315 |c.lw     | crdq  crs1q   cimmw  | cl·lw     | rv32c rv64c | vls  |
 316 |c.flw    | cfrdq crs1q   cimmw  | cl·lw+f   | rv32c       | vls  |
 317 |c.fsd    | crs1q cfrs2q  cimmd  | cs·sd+f   | rv32c rv64c | vls  |
 318 |c.sw     | crs1q crs2q   cimmw  | cs·sw     | rv32c rv64c | vls  |
 319 |c.fsw    | crs1q cfrs2q  cimmw  | cs·sw+f   | rv32c       | vls  |
 320 |c.nop    |                      | ci·none   | rv32c rv64c | - |
 321 |c.addi   | crs1rd      cnzimmi  | ci        | rv32c rv64c | sv  |
 322 |c.jal    |               cimmj  | cj·jal    | rv32c       | - |
 323 |c.li     | crs1rd        cimmi  | ci·li     | rv32c rv64c | sv  |
 324 |c.addi16sp|crs1rd     cimm16sp  | ci·16sp   | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) |
 325 |c.lui    | crd          cimmui  | ci·lui    | rv32c rv64c | sv |
 326 |c.srli   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 327 |c.srai   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 328 |c.andi   | crs1rdq     cnzimmi  | cb·imm    | rv32c rv64c | sv  |
 329 |c.sub    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 330 |c.xor    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 331 |c.or     | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 332 |c.and    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 333 |c.subw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 334 |c.addw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 335 |c.j      |               cimmj  | cj        | rv32c rv64c | - |
 336 |c.beqz   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 337 |c.bnez   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 338 |c.slli   | crs1rd      cimmsh5  | ci·sh5    | rv32c       | sv  |
 339 |c.fldsp  | cfrd       cimmldsp  | ci·ldsp+f | rv32c rv64c | VU  |
 340 |c.lwsp   | crd        cimmlwsp  | ci·lwsp   | rv32c rv64c | VU  |
 341 |c.flwsp  | cfrd       cimmlwsp  | ci·lwsp+f | rv32c       | VU  |
 342 |c.jr     | crd0 crs1            | cr·jr     | rv32c rv64c | - |
 343 |c.mv     | crd crs2             | cr·mv     | rv32c rv64c | 2v  |
 344 |c.ebreak |                      | ci·none   | rv32c rv64c | - |
 345 |c.jalr   | crd0 crs1            | cr·jalr   | rv32c rv64c | - |
 346 |c.add    | crs1rd crs2          | cr        | rv32c rv64c | sv  |
 347 |c.fsdsp  | cfrs2      cimmsdsp  | css·sdsp+f | rv32c rv64c | VU  |
 348 |c.swsp   | crs2       cimmswsp  | css·swsp  | rv32c rv64c | VU  |
 349 |c.fswsp  | cfrs2      cimmswsp  | css·swsp+f | rv32c      | VU  |
 350
 351 # RV64C    "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)"
 352
 353 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 354 | -------- | -------- | ------- | ------- |  |
 355 |c.ld     | crdq  crs1q   cimmd  | cl·ld           | rv64c | vls  |
 356 |c.sd     | crs1q crs2q   cimmd  | cs·sd           | rv64c | vls  |
 357 |c.addiw  | crs1rd        cimmi  | ci              | rv64c | sv  |
 358 |c.srli   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 359 |c.srai   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 360 |c.slli   | crs1rd      cimmsh6  | ci·sh6          | rv64c | sv  |
 361 |c.ldsp   | crd        cimmldsp  | ci·ldsp         | rv64c | VU  |
 362 |c.sdsp   | crs2       cimmsdsp  | css·sdsp        | rv64c | VU  |
 363
 364 # RV128C   "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)"
 365
 366 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 367 | -------- | -------- | ------- | ------- |  |
 368 |c.lq     | crdq crs1q    cimmq  | cl·lq           | rv128c | vls  |
 369 |c.sq     | crs1q crs2q   cimmq  | cs·sq           | rv128c | vls  |
 370 |c.lqsp   | crd        cimmlqsp  | ci·lqsp         | rv128c | VU  |
 371 |c.sqsp   | crs2       cimmsqsp  | css·sqsp        | rv128c | VU  |