simple_v_extension/opcodes.mdwn

   1 # SimpleV Instruction Categorisation
   2
   3 Based on information from Michael Clark's riscv-meta opcodes table
   4 (with thanks to Michael for creating it), this
   5 page categorises and identifies the type of parallelism that SimpleV
   6 indirectly adds on each RISC-V **standard** opcode.  These are note-form:
   7 see [[specification]] for full details.
   8
   9 * **-** no change of behaviour takes place: operation remains
  10   **completely scalar** as an **unmodified**, unaugmented standard RISC-V
  11   opcode, even if it has registers.
  12 * **sv** - a standard contiguous (optionally predicated, optionally
  13   indirected) multi-register operation where the predication register
  14   to be used for the sequence of contiguous operations is taken from the
  15   **destination** register's predication lookup entry.
  16 * **2v** - a standard contiguous (optionally twin-predicated, optionally
  17   indirected) twin-register operation (distinct source and destination)
  18   where either or both of source or destination may be redirected,
  19   vectorised, or **independently** predicated.  This behaviour
  20   covers the *entire* VMV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
  21   paradigm.
  22 * **vld** - a standard contiguous (optionally twin-predicated, optionally
  23   indirected) multi-register load operation where either or both of
  24   destination register or load-from-address register may be redirected,
  25   vectorised or **independently** predicated (LD.X style functionality).
  26   (*Note: Vector "Unit Stride" and "Constant Stride" may be emulated by
  27   pre-prepping a contiguous block of load-from-address registers with
  28   the appropriate address offsets*)
  29 * **vst** - a matching multi-register store operation with orthogonal
  30   functionality to  **vld**.
  31 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
  32   source-address register number being (optionally) incremented
  33   (and redirected, and predicated) it is the **immediate offset**
  34   that is incremented (by the element width of the **source** register)
  35 * **VSU** - a similarly "Unit Strided" variant of **vst**.
  36 * **VBR** - a standard branch operation (optionally predicated, optionally
  37   indirected) multi-register operation where the (optional) predication for the
  38   compare is taken from the destination register, and where (optionally)
  39   if the results of the multi-comparison are to be recorded, the **source**
  40   register's predication table entry is used as the means to specify
  41   (in a bitfield format that is directly compatible for follow-up use as a
  42   predicate) the register in which the comparison results are stored.
  43   On completion of all compares, if the tests carried out succeeded
  44   (de-predicated compares not being included in this assessment, evidently),
  45   the branch operation is carried out.
  46
  47 # RV32I/RV64I/RV128I    "RV32I/RV64I/RV128I Base Integer Instruction Set"
  48
  49 | (23..18) | (17..12) | (11..6) | (5...0) |  |
  50 | -------- | -------- | ------- | ------- |  |
  51 |auipc    | rd oimm20       | u+o  | rv32i rv64i rv128i | -  |
  52 |jal      | rd jimm20       | uj   | rv32i rv64i rv128i | -  |
  53 |jalr     | rd rs1 oimm12   | i+o  | rv32i rv64i rv128i | -  |
  54 |fence    |                 | r·f | rv32i rv64i rv128i | -  |
  55 |fence.i  |                 | none | rv32i rv64i rv128i | -  |
  56 |         |                 |       |                   |  |
  57 |lui      | rd imm20        | u     | rv32i rv64i rv128i | sv  |
  58 |         |                 |       |                   |  |
  59 |beq      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  60 |bne      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  61 |blt      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  62 |bge      | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  63 |bltu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  64 |bgeu     | rs1 rs2 sbimm12 | sb   | rv32i rv64i rv128i | VBR  |
  65 |         |                 |       |                   |  |
  66 |lb       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  67 |lh       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  68 |lw       | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  69 |lbu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  70 |lhu      | rd rs1 oimm12   | i+l  | rv32i rv64i rv128i | vld  |
  71 |lwu      | rd rs1 oimm12   |  i+l        | rv64i rv128i | vld  |
  72 |ld       | rd rs1 oimm12   |  i+l        | rv64i rv128i | vld  |
  73 |ldu      | rd rs1 oimm12  |   i+l              | rv128i | vld  |
  74 |lq       | rd rs1 oimm12  |   i+l              | rv128i | vld  |
  75 |         |                 |       |                   |  |
  76 |sb       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  77 |sh       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  78 |sw       | rs1 rs2 simm12  | s    | rv32i rv64i rv128i | vst  |
  79 |sd       | rs1 rs2 simm12  |  s          | rv64i rv128i | vst  |
  80 |sq       | rs1 rs2 simm12 |   s                | rv128i | vst  |
  81 |         |                 |       |                   |  |
  82 |addi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  83 |slti     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  84 |sltiu    | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  85 |xori     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  86 |ori      | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  87 |andi     | rd rs1 imm12    | i    | rv32i rv64i rv128i | sv  |
  88 |slli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  89 |srli     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  90 |srai     | rd rs1 shamt5   | i·sh5             | rv32i | sv  |
  91 |add      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  92 |sub      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  93 |sll      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  94 |slt      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  95 |sltu     | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  96 |xor      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  97 |srl      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  98 |sra      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
  99 |or       | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
 100 |and      | rd rs1 rs2      | r    | rv32i rv64i rv128i | sv  |
 101 |slli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
 102 |srli     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
 103 |srai     | rd rs1 shamt6   |  i·sh6             | rv64i | sv  |
 104 |addiw    | rd rs1 imm12    |  i          | rv64i rv128i | sv  |
 105 |slliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
 106 |srliw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
 107 |sraiw    | rd rs1 shamt5   |  i·sh5      | rv64i rv128i | sv  |
 108 |addw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
 109 |subw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
 110 |sllw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
 111 |srlw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
 112 |sraw     | rd rs1 rs2      |  r          | rv64i rv128i | sv  |
 113 |slli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
 114 |srli     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
 115 |srai     | rd rs1 shamt7  |   i·sh7            | rv128i | sv  |
 116 |addid    | rd rs1 imm12   |   i                | rv128i | sv  |
 117 |sllid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 118 |srlid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 119 |sraid    | rd rs1 shamt6  |   i·sh6            | rv128i | sv  |
 120 |addd     | rd rs1 rs2     |   r                | rv128i | sv  |
 121 |subd     | rd rs1 rs2     |   r                | rv128i | sv  |
 122 |slld     | rd rs1 rs2     |   r                | rv128i | sv  |
 123 |srld     | rd rs1 rs2     |   r                | rv128i | sv  |
 124 |srad     | rd rs1 rs2     |   r                | rv128i | sv  |
 125
 126 # RV32M    "RV32M Standard Extension for Integer Multiply and Divide"
 127
 128 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 129 | -------- | -------- | ------- | ------- |  |
 130 |mul      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 131 |mulh     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 132 |mulhsu   | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 133 |mulhu    | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 134 |div      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 135 |divu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 136 |rem      | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 137 |remu     | rd rs1 rs2   |     r    | rv32m rv64m rv128m | sv  |
 138
 139 # RV64M    "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
 140
 141 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 142 | -------- | -------- | ------- | ------- |  |
 143 |mulw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 144 |divw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 145 |divuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 146 |remw     | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 147 |remuw    | rd rs1 rs2   |     r          | rv64m rv128m | sv  |
 148
 149 # RV128M   "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
 150
 151 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 152 | -------- | -------- | ------- | ------- |  |
 153 |muld     | rd rs1 rs2   |     r                | rv128m | sv  |
 154 |divd     | rd rs1 rs2   |     r                | rv128m | sv  |
 155 |divud    | rd rs1 rs2   |     r                | rv128m | sv  |
 156 |remd     | rd rs1 rs2   |     r                | rv128m | sv  |
 157 |remud    | rd rs1 rs2   |     r                | rv128m | sv  |
 158
 159 # RV32A    "RV32A Standard Extension for Atomic Instructions"
 160
 161 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 162 | -------- | -------- | ------- | ------- |  |
 163 |lr.w     | rd rs1          | r·l | rv32a rv64a rv128a | -  |
 164 |sc.w     | rd rs1 rs2      | r·a | rv32a rv64a rv128a | -  |
 165 |         |                 |       |                   |  |
 166 |amoswap.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 167 |amoadd.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 168 |amoxor.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 169 |amoor.w  | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 170 |amoand.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 171 |amomin.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 172 |amomax.w | rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 173 |amominu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 174 |amomaxu.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a | sv  |
 175
 176 # RV64A    "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
 177
 178 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 179 | -------- | -------- | ------- | ------- |  |
 180 |lr.d     | rd rs1          | r·l      | rv64a rv128a | - |
 181 |sc.d     | rd rs1 rs2      | r·a      | rv64a rv128a | - |
 182 |         |                 |       |                   |  |
 183 |amoswap.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 184 |amoadd.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 185 |amoxor.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 186 |amoor.d  | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 187 |amoand.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 188 |amomin.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 189 |amomax.d | rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 190 |amominu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 191 |amomaxu.d| rd rs1 rs2      | r·a      | rv64a rv128a | sv  |
 192
 193 # RV128A   "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
 194
 195 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 196 | -------- | -------- | ------- | ------- |  |
 197 |lr.q     | rd rs1          | r·l | rv128a | - |
 198 |sc.q     | rd rs1 rs2      | r·a | rv128a | - |
 199 |         |                 |       |                   |  |
 200 |amoswap.q| rd rs1 rs2      | r·a | rv128a | sv  |
 201 |amoadd.q | rd rs1 rs2      | r·a | rv128a | sv  |
 202 |amoxor.q | rd rs1 rs2      | r·a | rv128a | sv  |
 203 |amoor.q  | rd rs1 rs2      | r·a | rv128a | sv  |
 204 |amoand.q | rd rs1 rs2      | r·a | rv128a | sv  |
 205 |amomin.q | rd rs1 rs2      | r·a | rv128a | sv  |
 206 |amomax.q | rd rs1 rs2      | r·a | rv128a | sv  |
 207 |amominu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 208 |amomaxu.q| rd rs1 rs2      | r·a | rv128a | sv  |
 209
 210 # RV32S    "RV32S Standard Extension for Supervisor-level Instructions"
 211
 212 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 213 | -------- | -------- | ------- | ------- |  |
 214 |ecall     |                         | none    | rv32s rv64s rv128s | - |
 215 |ebreak    |                         | none    | rv32s rv64s rv128s | - |
 216 |uret      |                         | none    | rv32s rv64s rv128s | - |
 217 |sret      |                         | none    | rv32s rv64s rv128s | - |
 218 |hret      |                         | none    | rv32s rv64s rv128s | - |
 219 |mret      |                         | none    | rv32s rv64s rv128s | - |
 220 |dret      |                         | none    | rv32s rv64s rv128s | - |
 221 |sfence.vm |         rs1             | r+sf    | rv32s rv64s rv128s | - |
 222 |sfence.vma| rs1 rs2                 | r+sfa   | rv32s rv64s rv128s | - |
 223 |wfi       |                         | none    | rv32s rv64s rv128s | - |
 224 |         |                 |       |                   |  |
 225 |csrrw     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 226 |csrrs     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 227 |csrrc     | rd      rs1      csr12  | i·csr   | rv32s rv64s rv128s | ? |
 228 |csrrwi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 229 |csrrsi    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 230 |csrrci    | rd      zimm     csr12  | i·csr+i | rv32s rv64s rv128s | ? |
 231
 232 # RV32F    "RV32F Standard Extension for Single-Precision Floating-Point"
 233
 234 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 235 | -------- | -------- | ------- | ------- | |
 236 |flw      | frd rs1           oimm12      | i+lf  | rv32f rv64f rv128f | vld  |
 237 |fsw      | rs1 frs2          simm12      | s+f   | rv32f rv64f rv128f | vld  |
 238 |         |                 |       |                   |  |
 239 |fmadd.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 240 |fmsub.s  | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 241 |fnmsub.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 242 |fnmadd.s | frd frs1 frs2 frs3         rm | r4·m  | rv32f rv64f rv128f | sv  |
 243 |fadd.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 244 |fsub.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 245 |fmul.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 246 |fdiv.s   | frd frs1 frs2              rm | r·m+3f | rv32f rv64f rv128f | sv  |
 247 |fmin.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 248 |fmax.s   | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | sv  |
 249 |fsqrt.s  | frd frs1                   rm | r·m+ff | rv32f rv64f rv128f | sv  |
 250 |fle.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 251 |flt.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 252 |feq.s    | rd frs1 frs2                  | r+rff | rv32f rv64f rv128f | sv  |
 253 |fclass.s | rd frs1                       | r+rf  | rv32f rv64f rv128f | sv  |
 254 |fsgnj.s  | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 255 |fsgnjn.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 256 |fsgnjx.s | frd frs1 frs2                 | r+3f  | rv32f rv64f rv128f | 2v  |
 257 |fcvt.w.s | rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 258 |fcvt.wu.s| rd frs1                    rm | r·m+rf | rv32f rv64f rv128f | 2v  |
 259 |fcvt.s.w | frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 260 |fcvt.s.wu| frd rs1                    rm | r·m+fr | rv32f rv64f rv128f | 2v  |
 261 |fmv.x.s  | rd frs1                       | r+rf  | rv32f rv64f rv128f | 2v  |
 262 |fmv.s.x  | frd rs1                       | r+fr  | rv32f rv64f rv128f | 2v  |
 263
 264 # RV64F    "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
 265
 266 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 267 | -------- | -------- | ------- | ------- |  |
 268 |fcvt.l.s | rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 269 |fcvt.lu.s| rd frs1  rm  |     r·m+rf      | rv64f rv128f | 2v  |
 270 |fcvt.s.l | frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 271 |fcvt.s.lu| frd rs1  rm  |     r·m+fr      | rv64f rv128f | 2v  |
 272
 273 # RV32D    "RV32D Standard Extension for Double-Precision Floating-Point"
 274
 275 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 276 | -------- | -------- | ------- | ------- |  |
 277 |fld      | frd rs1   oimm12      | i+lf  | rv32d rv64d rv128d | vld  |
 278 |fsd      | rs1 frs2  simm12      | s+f   | rv32d rv64d rv128d | vld  |
 279 |         |                 |       |                   |  |
 280 |fmadd.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 281 |fmsub.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 282 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 283 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d | sv  |
 284 |fadd.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 285 |fsub.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 286 |fmul.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 287 |fdiv.d   | frd frs1 frs2      rm | r·m+3f | rv32d rv64d rv128d | sv  |
 288 |fmin.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 289 |fmax.d   | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | sv  |
 290 |fsqrt.d  | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | sv  |
 291 |fle.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 292 |flt.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 293 |feq.d    | rd frs1 frs2          | r+rff | rv32d rv64d rv128d | sv  |
 294 |fclass.d | rd frs1               | r+rf  | rv32d rv64d rv128d | sv  |
 295 |         |                 |       |                   |  |
 296 |fsgnj.d  | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 297 |fsgnjn.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 298 |fsgnjx.d | frd frs1 frs2         | r+3f  | rv32d rv64d rv128d | 2v  |
 299 |fcvt.s.d | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 300 |fcvt.d.s | frd frs1 rm           | r·m+ff | rv32d rv64d rv128d | 2v  |
 301 |fcvt.w.d | rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 302 |fcvt.wu.d| rd frs1  rm           | r·m+rf | rv32d rv64d rv128d | 2v  |
 303 |fcvt.d.w | frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 304 |fcvt.d.wu| frd rs1  rm           | r·m+fr | rv32d rv64d rv128d | 2v  |
 305
 306 # RV64D    "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
 307
 308 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 309 | -------- | -------- | ------- | ------- |  |
 310 |fcvt.l.d | rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 311 |fcvt.lu.d| rd frs1  rm      | r·m+rf      | rv64d rv128d | 2v  |
 312 |fmv.x.d  | rd frs1          | r+rf        | rv64d rv128d | 2v  |
 313 |fcvt.d.l | frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 314 |fcvt.d.lu| frd rs1  rm      | r·m+fr      | rv64d rv128d | 2v  |
 315 |fmv.d.x  | frd rs1          | r+fr        | rv64d rv128d | 2v  |
 316
 317 # RV32Q    "RV32Q Standard Extension for Quad-Precision Floating-Point"
 318
 319 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 320 | -------- | -------- | ------- | ------- |  |
 321 |flq      | frd rs1       oimm12  | i+lf   | rv32q rv64q rv128q | vld  |
 322 |         |                 |       |                   |  |
 323 |fsq      | rs1 frs2      simm12  | s+f    | rv32q rv64q rv128q | vst  |
 324 |         |                 |       |                   |  |
 325 |fmadd.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 326 |fmsub.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 327 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 328 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q | sv  |
 329 |fadd.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 330 |fsub.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 331 |fmul.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 332 |fdiv.q   | frd frs1 frs2     rm  | r·m+3f | rv32q rv64q rv128q | sv  |
 333 |fmin.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 334 |fmax.q   | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | sv  |
 335 |fsqrt.q  | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | sv  |
 336 |fle.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 337 |flt.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 338 |feq.q    | rd frs1 frs2          | r+rff  | rv32q rv64q rv128q | sv  |
 339 |fclass.q | rd frs1               | r+rf   | rv32q rv64q rv128q | sv  |
 340 |         |                 |       |                   |  |
 341 |fsgnj.q  | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 342 |fsgnjn.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 343 |fsgnjx.q | frd frs1 frs2         | r+3f   | rv32q rv64q rv128q | 2v  |
 344 |fcvt.s.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 345 |fcvt.q.s | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 346 |fcvt.d.q | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 347 |fcvt.q.d | frd frs1 rm           | r·m+ff | rv32q rv64q rv128q | 2v  |
 348 |fcvt.w.q | rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 349 |fcvt.wu.q| rd frs1  rm           | r·m+rf | rv32q rv64q rv128q | 2v  |
 350 |fcvt.q.w | frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 351 |fcvt.q.wu| frd rs1  rm           | r·m+fr | rv32q rv64q rv128q | 2v  |
 352
 353 # RV64Q    "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
 354
 355 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 356 | -------- | -------- | ------- | ------- |  |
 357 |fcvt.l.q | rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 358 |fcvt.lu.q| rd frs1  rm       | r·m+rf        | rv64q rv128q | 2v  |
 359 |fcvt.q.l | frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 360 |fcvt.q.lu| frd rs1  rm       | r·m+fr        | rv64q rv128q | 2v  |
 361
 362 # RV128Q   "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
 363
 364 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 365 | -------- | -------- | ------- | ------- |  |
 366 |fmv.x.q  | rd frs1  | r+rf          | rv64q rv128q | 2v  |
 367 |fmv.q.x  | frd rs1  | r+fr          | rv64q rv128q | 2v  |
 368
 369 # RV32C/RV64C/RV128C    "RV32C/RV64C/RV128C Standard Extension for Compressed Instructions"
 370
 371 | (23..18) | (17..12) | (11..6) | (5...0) |  |
 372 | -------- | -------- | ------- | ------- |  |
 373 |c.addi4spn|crdq       cimm4spn  | ciw·4spn  | rv32c rv64c | - |
 374 |c.nop    |                      | ci·none   | rv32c rv64c | - |
 375 |c.jal    |               cimmj  | cj·jal    | rv32c       | - |
 376 |c.j      |               cimmj  | cj        | rv32c rv64c | - |
 377 |c.jr     | crd0 crs1            | cr·jr     | rv32c rv64c | - |
 378 |c.ebreak |                      | ci·none   | rv32c rv64c | - |
 379 |c.jalr   | crd0 crs1            | cr·jalr   | rv32c rv64c | - |
 380 |         |                 |       |                   |  |
 381 |c.mv     | crd crs2             | cr·mv     | rv32c rv64c | 2v  |
 382 |         |                 |       |                   |  |
 383 |c.fld    | cfrdq crs1q   cimmd  | cl·ld+f   | rv32c rv64c | vld  |
 384 |c.lw     | crdq  crs1q   cimmw  | cl·lw     | rv32c rv64c | vld  |
 385 |c.flw    | cfrdq crs1q   cimmw  | cl·lw+f   | rv32c       | vld  |
 386 |c.ld     | crdq  crs1q   cimmd  | cl·ld           | rv64c | vld  |
 387 |c.lq     | crdq crs1q    cimmq  | cl·lq           | rv128c | vld  |
 388 |         |                 |       |                   |  |
 389 |c.fsd    | crs1q cfrs2q  cimmd  | cs·sd+f   | rv32c rv64c | vst  |
 390 |c.sw     | crs1q crs2q   cimmw  | cs·sw     | rv32c rv64c | vst  |
 391 |c.fsw    | crs1q cfrs2q  cimmw  | cs·sw+f   | rv32c       | vst  |
 392 |c.sd     | crs1q crs2q   cimmd  | cs·sd           | rv64c | vst  |
 393 |c.sq     | crs1q crs2q   cimmq  | cs·sq           | rv128c | vst  |
 394 |         |                 |       |                   |  |
 395 |c.addi16sp|crs1rd     cimm16sp  | ci·16sp   | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) |
 396 |c.addi   | crs1rd      cnzimmi  | ci        | rv32c rv64c | sv  |
 397 |c.li     | crs1rd        cimmi  | ci·li     | rv32c rv64c | sv  |
 398 |c.lui    | crd          cimmui  | ci·lui    | rv32c rv64c | sv |
 399 |c.srli   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 400 |c.srai   | crs1rdq     cimmsh5  | cb·sh5    | rv32c       | sv  |
 401 |c.slli   | crs1rd      cimmsh5  | ci·sh5    | rv32c       | sv  |
 402 |c.andi   | crs1rdq     cnzimmi  | cb·imm    | rv32c rv64c | sv  |
 403 |c.sub    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 404 |c.xor    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 405 |c.or     | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 406 |c.and    | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 407 |c.subw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 408 |c.addw   | crs1rdq crs2q        | cs        | rv32c rv64c | sv  |
 409 |c.add    | crs1rd crs2          | cr        | rv32c rv64c | sv  |
 410 |c.addiw  | crs1rd        cimmi  | ci              | rv64c | sv  |
 411 |c.srli   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 412 |c.srai   | crs1rdq     cimmsh6  | cb·sh6          | rv64c | sv  |
 413 |c.slli   | crs1rd      cimmsh6  | ci·sh6          | rv64c | sv  |
 414 |         |                 |       |                   |  |
 415 |c.beqz   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 416 |c.bnez   | crs1q         cimmb  | cb        | rv32c rv64c | VBR  |
 417 |         |                 |       |                   |  |
 418 |c.fldsp  | cfrd       cimmldsp  | ci·ldsp+f | rv32c rv64c | VLU  |
 419 |c.lwsp   | crd        cimmlwsp  | ci·lwsp   | rv32c rv64c | VLU  |
 420 |c.flwsp  | cfrd       cimmlwsp  | ci·lwsp+f | rv32c       | VLU  |
 421 |c.ldsp   | crd        cimmldsp  | ci·ldsp         | rv64c | VLU  |
 422 |c.lqsp   | crd        cimmlqsp  | ci·lqsp         | rv128c | VLU  |
 423 |         |                 |       |                   |  |
 424 |c.fsdsp  | cfrs2      cimmsdsp  | css·sdsp+f | rv32c rv64c | VSU  |
 425 |c.swsp   | crs2       cimmswsp  | css·swsp  | rv32c rv64c | VSU  |
 426 |c.fswsp  | cfrs2      cimmswsp  | css·swsp+f | rv32c      | VSU  |
 427 |c.sdsp   | crs2       cimmsdsp  | css·sdsp        | rv64c | VSU  |
 428 |c.sqsp   | crs2       cimmsqsp  | css·sqsp        | rv128c | VSU  |