simple_v_extension/open_3d_alliance_2019aug26.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
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   4 \usepackage{pstricks}
   5
   6 \title{Open 3D Alliance RISC-V}
   7 \author{Luke Kenneth Casson Leighton}
   8
   9
  10 \begin{document}
  11
  12 \frame{
  13    \begin{center}
  14     \huge{Open 3D Alliance: RISC-V}\\
  15     \vspace{32pt}
  16     \Large{An open invitation to collaborate on 3D Graphics}\\
  17     \Large{Hardware and Software}\\
  18     \Large{for mobile, embedded, and innovative purposes}\\
  19     \vspace{24pt}
  20     \Large{With thanks to Pixilica, GoWin, and Western Digital}\\
  21     \vspace{16pt}
  22     \large{\today}
  23   \end{center}
  24 }
  25
  26
  27 \frame{\frametitle{Why collaborate?}
  28
  29  \begin{itemize}
  30    \item 3D is hard. It's also not the same as HPC\vspace{15pt}
  31    \item NVIDIA, AMD, Imagination - cannot meet "unusual" needs\vspace{15pt}
  32    \item Working together on flexible standards, everyone wins\vspace{15pt}
  33    \item Without collaboration: 10-20 man-years development\vspace{10pt}
  34    \item With collaboration: cross-verification (avoids mistakes)
  35   \end{itemize}
  36 }
  37
  38
  39 \frame{\frametitle{What is the goal?}
  40
  41  \begin{itemize}
  42    \item You get to decide! No, really!\vspace{12pt}
  43    \item Outlined here: some ideas and cost/time-saving approaches\vspace{12pt}
  44    \item Two new platforms: 3D "Embedded", 3D "UNIX"\vspace{12pt}
  45    \item Flexible optional extensions (Transcendentals, Vectors,\\
  46                  Texturisation, Pixel/Z-Buffers - all optional)\vspace{12pt}
  47    \item Good software support absolutely essential\\
  48              (basically, that means Vulkan)\vspace{15pt}
  49   \end{itemize}
  50 }
  51
  52 \frame{\frametitle{Libre RISC-V Team}
  53
  54  \begin{itemize}
  55    \item Small team, sponsored by Purism and the NLNet Foundation\vspace{8pt}
  56    \item Therefore, focus is on efficiency: leap-frogging ahead\\
  57              without requiring huge resources.\vspace{8pt}
  58    \item OpenGL API? Gallium3D / Vulkan is better\vspace{8pt}
  59    \item Gallium3D turns out to be a single-threaded interpreter\\
  60              (Vulkan is compiled, and can be parallelised)\vspace{8pt}
  61    \item Independent teams have provided OpenGL to Vulkan adaptors\vspace{8pt}
  62    \item Same approach on hardware: seek highest bang-per-buck\\
  63                  Save design time, save implementation time\vspace{8pt}
  64   \end{itemize}
  65 }
  66
  67 \frame{\frametitle{What (optional) things are needed?}
  68
  69  \begin{itemize}
  70    \item Vectorisation.  (SIMD? RVV? Other?)\vspace{12pt}
  71    \item Transcendentals (SIN, COS, EXP, LOG)\vspace{12pt}
  72    \item Texture opcodes, Pixel/Z-Buffers\vspace{12pt}
  73    \item Pixel conversion (YUV/RGB etc.)\vspace{12pt}
  74    \item Optional accuracy (embedded space needs less accuracy)\vspace{12pt}
  75    \item Options give implementors flexibility.  No imposition:\\
  76          imposition risks fragmentation (however, collaboration does\\
  77          need some hard easily-logically-justifiable rules)
  78   \end{itemize}
  79 }
  80
  81 \frame{\frametitle{What is essential (not really optional)}
  82
  83  \begin{itemize}
  84    \item The software, basically.  Anything other than Vulkan\\
  85              is a 10+ man-year effort\vspace{12pt}
  86    \item Respecting that standards are hard to get right\\
  87          (and that consequences of mistakes are severe:\\
  88          no opportunity for corrections after a freeze)\vspace{12pt}
  89    \item Respecting that, for collaboration and interoperability,\\
  90          some things go into a standard that you might not "need"\vspace{12pt}
  91    \item Mutually respectful open and fully transparent collaboration.\\
  92          No NDAs, no "closed forums".  We need the help of experts\\
  93          (such as Mitch Alsup) in this highly technical specialist area.
  94   \end{itemize}
  95 }
  96
  97 \frame{\frametitle{What has our team done already?}
  98
  99  \begin{itemize}
 100    \item Decided to go the "Hybrid" Route (Separate GPUs requires a\\
 101          full-blown RPC/IPC mechanism to transfer all 3D API calls\\
 102          to and from userspace memory to GPU memory... and back).
 103    \item Developed Simple-V (a "Parallelising API)\\
 104                  (Simple-V is very hard to describe, because it is unique:\\
 105                  there is no common Computer Science terminology)
 106    \item Started on Kazan (a Vulkan SPIR-V to LLVM compiler)
 107    \item Started work on a highly flexible IEEE754 FPU
 108    \item Started work on a "Precise" CDC 6600 style OoO Engine,\\
 109              with help from Mitch Alsup, the designer of the M68000
 110    \item Variable-issue, predicated SIMD backend, Vector front-end\\
 111              "precise" exceptions, branch shadowing, much more
 112   \end{itemize}
 113 }
 114
 115 \frame{\frametitle{Why Simple-V? Why not RVV?}
 116
 117  \begin{itemize}
 118    \item RVV is designed exclusively for supercomputing\vspace{8pt}
 119    \item Like SIMD, RVV uses dedicated opcodes\\
 120              (google "SIMD considered harmful")\vspace{8pt}
 121    \item 98\% of FP opcodes are duplicated in RVV. Large portion\\
 122          of BitManip opcodes duplicated in predicate Masks\vspace{8pt}
 123    \item OP32 space is extremely precious: 48 and 64 bit opcode space\\
 124          comes with an inherent I-Cache power consumption penalty\vspace{8pt}
 125    \item Simple-V "prefixes" scalar opcodes (all of them)\\
 126              No need for any new "vector" opcodes (at all).\\
 127              Can therefore use the RVV major opcode for 3D\vspace{8pt}
 128   \end{itemize}
 129 }
 130
 131 \frame{\frametitle{Simple-V "Prefixing"}
 132
 133  \begin{itemize}
 134    \item SV "Prefix" does exactly that: takes RVC and OP32 opcodes\\
 135          and "prefixes" them with predication and a "vector" tag\vspace{8pt}
 136    \item Three prefix types: SV P32 (prefixed RVC), P48 and P64\vspace{8pt}
 137    \item Prefixed RVC takes 3 "Custom" OP32 opcodes.\\
 138              P48 takes standard OP32 scalar opcodes and "prefixes" them\\
 139              P64 adds additional vector context on top of P48\\
 140              \vspace{8pt}
 141    \item "Prefixing" is a bit like SIMD.  Vectors may be specified\\
 142              of length 2 to 4, elements may be "packed" into registers,\\
 143              opcode element widths over-ridden.\vspace{8pt}
 144    \item Convenient, but not very space-efficient (and VBLOCK is)\vspace{8pt}
 145   \end{itemize}
 146 }
 147
 148 \frame{\frametitle{VBLOCK Format}
 149
 150  \begin{itemize}
 151    \item Again: hard to describe.  It is a bit like VLIW (only not really)\\
 152              A "block" of instructions is "prefixed" with register "tags"\\
 153                  which give extra context to scalar instructions within the block
 154   \item Sub-blocks include: Vector Length, Swizzling, Vector/Width\\
 155          overrides, and predication.  All this is added to scalar opcodes!\\
 156          \textbf{There are NO vector opcodes} (and no need for any)
 157    \item In the "context", it goes like this: "if a register is used\\
 158          by a scalar opcode, and the register is listed in the "context",\\
 159          SV mode is "activated"
 160    \item "Activation" results in a hardware-level "for-loop" issuing\\
 161          \textbf{multiple} contiguous scalar operations (instead of just one).
 162    \item Implementors are free to implement the "loop" in any fashion\\
 163          they see fit.  SIMD, Multi-issue, single-execution: anything.
 164   \end{itemize}
 165 }
 166
 167 \frame{\frametitle{Other Standard Proposals}
 168
 169  \begin{itemize}
 170    \item Ztrans and Ztrig* - Transcendentals and Trigonometrics\\
 171          (optional so that Embedded implementors have some leeway)
 172    \item ISAMUX / ISANS - stops arguments over OP32 space\\
 173          (also allows clean "paging" of new opcodes into e.g. RVC)
 174    \item MV.SWIZZLE and MV.X - RV does not have a MV opcode.
 175    \item Zfacc - dynamic FP accuracy.  Needed for "fast" Vulkan native\\
 176              and to switch between fast 3D accuracy and IEEE754 modes.
 177    \item These - and more - need your input! 3D is hard!
 178    \item The key strategic premise: these are required as \textbf{public}\\
 179          standards, because the \textbf{software} is to be public.
 180    \item This is \textbf{not} understood by the RISC-V Foundation.\\
 181          ("custom" status not appropriate for high-profile mass-volume\\
 182          end-user APIs such as Vulkan).
 183   \end{itemize}
 184 }
 185
 186
 187 \frame{\frametitle{Summary}
 188
 189  \begin{itemize}
 190    \item 3D is hard (and pure Vectorisation gets you 25\% of \\
 191          commercially-acceptable performance).
 192    \item Layered optional extensions are going to be key to\\
 193          acceptance by a wide variety of 3D Alliance Members.
 194    \item With a custom specialised SPIR-V (Vulkan) Compiler\\
 195          being an absolutely critical strategic requirement,\\
 196          RVV and its associated compiler (still not developed)\\
 197          is, surprisingly, of marginal value.
 198    \item Question everything!  Your input, and a willingness to\\
 199              take active responsibility for tasks that your Company\\
 200              is critically dependent on, are extremely important.
 201    \item Public and transparent Collaboration is key.  There is simply\\
 202          too much to do.
 203   \end{itemize}
 204 }
 205
 206
 207 \frame{
 208   \begin{center}
 209     {\Huge \vspace{20pt}
 210                    The end\vspace{20pt}\\
 211                    Thank you\vspace{20pt}\\
 212         }
 213   \end{center}
 214
 215   \begin{itemize}
 216         \item http://lists.libre-riscv.org/pipermail/libre-riscv-dev/
 217         \item http://libre-riscv.org/simple\_v\_extension/abridged\_spec/
 218         \item https://libre-riscv.org/ztrans\_proposal/
 219         \item https://libre-riscv.org/simple\_v\_extension/specification/mv.x/
 220   \end{itemize}
 221 }
 222
 223
 224 \end{document}