simple_v_extension/pred_table_format.mdwn

   1 16 bit format:
   2
   3 | PrCSR | (15..11) | 10     | 9     | 8   | (7..1)  | 0       |
   4 | ----- | -        | -      | -     | -   | ------- | ------- |
   5 | 0     | predidx  | zero0  | inv0  | i/f | regidx  | ffirst0 |
   6 | 1     | predidx  | zero1  | inv1  | i/f | regidx  | ffirst1 |
   7 | 2     | predidx  | zero2  | inv2  | i/f | regidx  | ffirst2 |
   8 | 3     | predidx  | zero3  | inv3  | i/f | regidx  | ffirst3 |
   9
  10 Note: predidx=x0, zero=1, inv=1 is a RESERVED encoding.  Its use must
  11 generate an illegal instruction trap.
  12
  13 8 bit format:
  14
  15 | PrCSR | 7     | 6     | 5   | (4..0)  |
  16 | ----- | -     | -     | -   | ------- |
  17 | 0     | zero0 | inv0  | i/f | regnum  |
  18
  19 Mapping from 8 to 16 bit format, the table becomes:
  20
  21 | PrCSR | (15..11) | 10     | 9     | 8   | (7..1)  | 0       |
  22 | ----- | -        | -      | -     | -   | ------- | ------- |
  23 | 0     | x9       | zero0  | inv0  | i/f | regnum  | ff=0    |
  24 | 1     | x10      | zero1  | inv1  | i/f | regnum  | ff=0    |
  25 | 2     | x11      | zero2  | inv2  | i/f | regnum  | ff=0    |
  26 | 3     | x12      | zero3  | inv3  | i/f | regnum  | ff=0    |
  27