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[libreriscv.git] / simple_v_extension / reg_table.mdwn
1 struct vectorised {
2 bool isvector:1;
3 int vew:2;
4 int predidx:7;
5 bool enabled:1;
6 }
7
8 struct vectorised fp_vec[32], int_vec[32];
9
10 for (i = 0; i < len; i++) // from VBLOCK Format
11 tb = int_vec if CSRvec[i].type == 0 else fp_vec
12 idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
13 tb[idx].elwidth = CSRvec[i].elwidth
14 tb[idx].regidx = CSRvec[i].regidx // indirection
15 tb[idx].isvector = CSRvec[i].isvector // 0=scalar
16 tb[idx].enabled = true;
17
18