simple_v_extension/remap.mdwn

   1 [[!tag standards]]
   2
   3 # NOTE
   4
   5 This section is under revision (and is optional)
   6
   7 # REMAP CSR <a name="remap" />
   8
   9 (Note: both the REMAP and SHAPE sections are best read after the
  10  rest of the document has been read)
  11
  12 There is one 32-bit CSR which may be used to indicate which registers,
  13 if used in any operation, must be "reshaped" (re-mapped) from a linear
  14 form to a 2D or 3D transposed form, or "offset" to permit arbitrary
  15 access to elements within a register.
  16
  17 The 32-bit REMAP CSR may reshape up to 3 registers:
  18
  19 | 29..28 | 27..26 | 25..24 | 23 | 22..16  | 15 | 14..8   | 7  | 6..0    |
  20 | ------ | ------ | ------ | -- | ------- | -- | ------- | -- | ------- |
  21 | shape2 | shape1 | shape0 | 0  | regidx2 | 0  | regidx1 | 0  | regidx0 |
  22
  23 regidx0-2 refer not to the Register CSR CAM entry but to the underlying
  24 *real* register (see regidx, the value) and consequently is 7-bits wide.
  25 When set to zero (referring to x0), clearly reshaping x0 is pointless,
  26 so is used to indicate "disabled".
  27 shape0-2 refers to one of three SHAPE CSRs.  A value of 0x3 is reserved.
  28 Bits 7, 15, 23, 30 and 31 are also reserved, and must be set to zero.
  29
  30 It is anticipated that these specialist CSRs not be very often used.
  31 Unlike the CSR Register and Predication tables, the REMAP CSRs use
  32 the full 7-bit regidx so that they can be set once and left alone,
  33 whilst the CSR Register entries pointing to them are disabled, instead.
  34
  35 # SHAPE 1D/2D/3D vector-matrix remapping CSRs
  36
  37 (Note: both the REMAP and SHAPE sections are best read after the
  38  rest of the document has been read)
  39
  40 There are three "shape" CSRs, SHAPE0, SHAPE1, SHAPE2, 32-bits in each,
  41 which have the same format.  When each SHAPE CSR is set entirely to zeros,
  42 remapping is disabled: the register's elements are a linear (1D) vector.
  43
  44 | 26..24  | 23      | 22..16  | 15      | 14..8   | 7       | 6..0    |
  45 | ------- | --      | ------- | --      | ------- | --      | ------- |
  46 | permute | offs[2] | zdimsz  | offs[1] | ydimsz  | offs[0] | xdimsz  |
  47
  48 offs is a 3-bit field, spread out across bits 7, 15 and 23, which
  49 is added to the element index during the loop calculation.
  50
  51 xdimsz, ydimsz and zdimsz are offset by 1, such that a value of 0 indicates
  52 that the array dimensionality for that dimension is 1.  A value of xdimsz=2
  53 would indicate that in the first dimension there are 3 elements in the
  54 array.  The format of the array is therefore as follows:
  55
  56     array[xdim+1][ydim+1][zdim+1]
  57
  58 However whilst illustrative of the dimensionality, that does not take the
  59 "permute" setting into account.  "permute" may be any one of six values
  60 (0-5, with values of 6 and 7 being reserved, and not legal).  The table
  61 below shows how the permutation dimensionality order works:
  62
  63 | permute | order | array format             |
  64 | ------- | ----- | ------------------------ |
  65 | 000     | 0,1,2 | (xdim+1)(ydim+1)(zdim+1) |
  66 | 001     | 0,2,1 | (xdim+1)(zdim+1)(ydim+1) |
  67 | 010     | 1,0,2 | (ydim+1)(xdim+1)(zdim+1) |
  68 | 011     | 1,2,0 | (ydim+1)(zdim+1)(xdim+1) |
  69 | 100     | 2,0,1 | (zdim+1)(xdim+1)(ydim+1) |
  70 | 101     | 2,1,0 | (zdim+1)(ydim+1)(xdim+1) |
  71
  72 In other words, the "permute" option changes the order in which
  73 nested for-loops over the array would be done.  The algorithm below
  74 shows this more clearly, and may be executed as a python program:
  75
  76     # mapidx = REMAP.shape2
  77     xdim = 3 # SHAPE[mapidx].xdim_sz+1
  78     ydim = 4 # SHAPE[mapidx].ydim_sz+1
  79     zdim = 5 # SHAPE[mapidx].zdim_sz+1
  80
  81     lims = [xdim, ydim, zdim]
  82     idxs = [0,0,0] # starting indices
  83     order = [1,0,2] # experiment with different permutations, here
  84     offs = 0        # experiment with different offsets, here
  85
  86     for idx in range(xdim * ydim * zdim):
  87         new_idx = offs + idxs[0] + idxs[1] * xdim + idxs[2] * xdim * ydim
  88         print new_idx,
  89         for i in range(3):
  90             idxs[order[i]] = idxs[order[i]] + 1
  91             if (idxs[order[i]] != lims[order[i]]):
  92                 break
  93             print
  94             idxs[order[i]] = 0
  95
  96 Here, it is assumed that this algorithm be run within all pseudo-code
  97 throughout this document where a (parallelism) for-loop would normally
  98 run from 0 to VL-1 to refer to contiguous register
  99 elements; instead, where REMAP indicates to do so, the element index
 100 is run through the above algorithm to work out the **actual** element
 101 index, instead.  Given that there are three possible SHAPE entries, up to
 102 three separate registers in any given operation may be simultaneously
 103 remapped:
 104
 105     function op_add(rd, rs1, rs2) # add not VADD!
 106       ...
 107       ...
 108       for (i = 0; i < VL; i++)
 109         xSTATE.srcoffs = i # save context
 110         if (predval & 1<<i) # predication uses intregs
 111            ireg[rd+remap(id)] <= ireg[rs1+remap(irs1)] +
 112                                  ireg[rs2+remap(irs2)];
 113            if (!int_vec[rd ].isvector) break;
 114         if (int_vec[rd ].isvector)  { id += 1; }
 115         if (int_vec[rs1].isvector)  { irs1 += 1; }
 116         if (int_vec[rs2].isvector)  { irs2 += 1; }
 117
 118 By changing remappings, 2D matrices may be transposed "in-place" for one
 119 operation, followed by setting a different permutation order without
 120 having to move the values in the registers to or from memory.  Also,
 121 the reason for having REMAP separate from the three SHAPE CSRs is so
 122 that in a chain of matrix multiplications and additions, for example,
 123 the SHAPE CSRs need only be set up once; only the REMAP CSR need be
 124 changed to target different registers.
 125
 126 Note that:
 127
 128 * Over-running the register file clearly has to be detected and
 129   an illegal instruction exception thrown
 130 * When non-default elwidths are set, the exact same algorithm still
 131   applies (i.e. it offsets elements *within* registers rather than
 132   entire registers).
 133 * If permute option 000 is utilised, the actual order of the
 134   reindexing does not change!
 135 * If two or more dimensions are set to zero, the actual order does not change!
 136 * The above algorithm is pseudo-code **only**.  Actual implementations
 137   will need to take into account the fact that the element for-looping
 138   must be **re-entrant**, due to the possibility of exceptions occurring.
 139   See MSTATE CSR, which records the current element index.
 140 * Twin-predicated operations require **two** separate and distinct
 141   element offsets.  The above pseudo-code algorithm will be applied
 142   separately and independently to each, should each of the two
 143   operands be remapped.  *This even includes C.LDSP* and other operations
 144   in that category, where in that case it will be the **offset** that is
 145   remapped (see Compressed Stack LOAD/STORE section).
 146 * Offset is especially useful, on its own, for accessing elements
 147   within the middle of a register.  Without offsets, it is necessary
 148   to either use a predicated MV, skipping the first elements, or
 149   performing a LOAD/STORE cycle to memory.
 150   With offsets, the data does not have to be moved.
 151 * Setting the total elements (xdim+1) times (ydim+1) times (zdim+1) to
 152   less than MVL is **perfectly legal**, albeit very obscure.  It permits
 153   entries to be regularly presented to operands **more than once**, thus
 154   allowing the same underlying registers to act as an accumulator of
 155   multiple vector or matrix operations, for example.
 156
 157 Clearly here some considerable care needs to be taken as the remapping
 158 could hypothetically create arithmetic operations that target the
 159 exact same underlying registers, resulting in data corruption due to
 160 pipeline overlaps.  Out-of-order / Superscalar micro-architectures with
 161 register-renaming will have an easier time dealing with this than
 162 DSP-style SIMD micro-architectures.
 163