simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 This proposal is designed to be able to operate without SVcsr, but not to
   5 require the absence of SVcsr.
   6
   7 Conventions
   8 ===========
   9
  10 Conventions used in this document:
  11 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  12 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  13
  14 Operations work on variable-length vectors of sub-vectors, where each sub-vector
  15 has a length *svlen*, and an element type *etype*. When the vectors are stored
  16 in registers, all elements are packed so that there is no padding in-between
  17 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
  18 product of *svlen* and the element size in bytes.
  19
  20 Half-Precision Floating Point (FP16)
  21 ====================================
  22 If the F extension is supported, SVprefix adds support for FP16 in the
  23 base FP instructions by using 10 (H) in the floating-point format field *fmt*
  24 and using 001 (H) in the floating-point load/store *width* field.
  25
  26 Compressed Instructions
  27 =======================
  28 This proposal doesn't include any prefixed RVC instructions, instead, it will
  29 include 32-bit instructions that are compressed forms of SVprefix 48-bit
  30 instructions, in the same manner that RVC instructions are compressed forms of
  31 RVI instructions. The compressed instructions will be defined later by
  32 considering which 48-bit instructions are the most common.
  33
  34 48-bit Prefixed Instructions
  35 ============================
  36 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
  37 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
  38 are reused for additional encoding space in the 48-bit instructions.
  39
  40 64-bit Prefixed Instructions
  41 ============================
  42
  43 The 48 bit format is further extended with the full 128-bit range on all source
  44 and destination registers, and the option to set both VL and MVL is provided.
  45
  46 48-bit Instruction Encodings
  47 ============================
  48
  49 In the following table, *Reserved* entries must be zero.  RV32 equivalent encodings
  50 included for side-by-side comparison (and listed below, separately).
  51
  52 First, bits 17:0:
  53
  54 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  55 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
  56 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  57 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  58 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  59 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  60 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  61 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
  62 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  63 | P48-I-type    | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  64 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  65 | P48-U-type    | rd[5]  | *Reserved* | *Reserved* | vd  | *Reserved* | vitp6              | *Reserved* | 011111 |
  66 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  67 | P48-FR-type   | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | *Reserved*  | vtp5 | *Reserved* | 011111 |
  68 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  69 | P48-FI-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  70 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  71 | P48-FR4-type  | rd[5]  | rs1[5]     | rs2[5]     | vs2 | rs3[5]     | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
  72 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  73
  74 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
  75           there is not enough space for vs1 as well, and because it is more
  76           useful to have a scalar argument for each of the multiplication and
  77           addition portions of fmadd than to have two scalars on the
  78           multiplication portion.
  79
  80 Table showing correspondance between P48-*-type and RV32-*-type.  These are
  81 bits 47:18 (RV32 shifted up by 16 bits):
  82
  83 +---------------+---------------+
  84 | Encoding      | 47:18         |
  85 +---------------+---------------+
  86 | RV32 Encoding | 31:2          |
  87 +---------------+---------------+
  88 | P48-LD-type   | RV32-I-type   |
  89 +---------------+---------------+
  90 | P48-ST-type   | RV32-S-Type   |
  91 +---------------+---------------+
  92 | P48-R-type    | RV32-R-Type   |
  93 +---------------+---------------+
  94 | P48-I-type    | RV32-I-Type   |
  95 +---------------+---------------+
  96 | P48-U-type    | RV32-U-Type   |
  97 +---------------+---------------+
  98 | P48-FR-type   | RV32-FR-Type  |
  99 +---------------+---------------+
 100 | P48-FI-type   | RV32-I-Type   |
 101 +---------------+---------------+
 102 | P48-FR4-type  | RV32-FR-type  |
 103 +---------------+---------------+
 104
 105 Table showing Standard RV32 encodings:
 106
 107 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 108 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
 109 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 110 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 111 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 112 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1      + 1          |
 113 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 114 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 115 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 116 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 1      + 1          |
 117 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 118 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 119 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 120 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 1      + 1          |
 121 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 122
 123 64-bit Instruction Encodings
 124 ============================
 125
 126 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
 127 now set to "0b0111111".
 128
 129 +---------------+---------------+--------------+-----------+
 130 | 63:48         | 47:18         | 17:7         | 6:0       |
 131 +---------------+---------------+--------------+-----------+
 132 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 133 +---------------+---------------+--------------+-----------+
 134
 135 * The 64 bit prefix format is below
 136 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 137 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 138 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 139
 140 64 bit prefix format:
 141
 142 +--------------+-------+--------+--------+--------+--------+
 143 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 144 +--------------+-------+--------+--------+--------+--------+
 145 | P64-LD-type  | rd[6] | rs1[6] |        |        | VLtyp  |
 146 +--------------+-------+--------+--------+--------+--------+
 147 | P64-ST-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 148 +--------------+-------+--------+--------+--------+--------+
 149 | P64-R-type   | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 150 +--------------+-------+--------+--------+--------+--------+
 151 | P64-I-type   | rd[6] | rs1[6] |        |        | VLtyp  |
 152 +--------------+-------+--------+--------+--------+--------+
 153 | P64-U-type   | rd[6] |        |        |        | VLtyp  |
 154 +--------------+-------+--------+--------+--------+--------+
 155 | P64-FR-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 156 +--------------+-------+--------+--------+--------+--------+
 157 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 158 +--------------+-------+--------+--------+--------+--------+
 159 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 160 +--------------+-------+--------+--------+--------+--------+
 161
 162 The extra bit for src and dest registers provides the full range of
 163 up to 128 registers, when combined with the extra bit from the 48 bit
 164 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 165
 166 VLtyp field encoding
 167 ====================
 168
 169 +-----------+-------------+--------------+----------+----------------------+
 170 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 171 +-----------+-------------+--------------+----------+----------------------+
 172 | 0         |  000000     | 00000        |  0       | no change to VL/MVL  |
 173 +-----------+-------------+--------------+----------+----------------------+
 174 | 0         |  VLdest!=0  | 00000        |  0       | reserved             |
 175 +-----------+-------------+--------------+----------+----------------------+
 176 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 177 +-----------+-------------+--------------+----------+----------------------+
 178 | 1         |  VLdest     |  MVL+VL-immed           | MVL/VL immed mode    |
 179 +-----------+-------------+--------------+----------+----------------------+
 180
 181 Notes:
 182
 183 * When VLtyp is all zeros, neither VL nor MVL are changed
 184 * VLtype[11]=0, VLtype[5:0]=0 and VLtype[10:6] non-zero is a reserved encoding.
 185   Its uses raises an illegal instruction exception.
 186
 187 Just as in the VLIW format, when bit 11 of VLtyp is zero:
 188
 189 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 190   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 191 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 192   from which VL is set.  x0 is not permitted
 193 * VL goes into the scalar register VLdest (if VLdest is not x0)
 194
 195 When bit 11 of VLtype is 1:
 196
 197 * both MAXVL and VL are set to (VLenimmed+1)
 198 * the same value goes into the scalar register VLdest (if VLdest is not x0)
 199
 200 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 201 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 202 same immediate value.  This may be most useful for one-off Vectorised
 203 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 204 of large batches of registers in context-switches or function calls.
 205
 206 vs#/vd Fields' Encoding
 207 =======================
 208
 209 +--------+----------+----------------------------------------------------------+
 210 | vs#/vd | Mnemonic | Meaning                                                  |
 211 +========+==========+==========================================================+
 212 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 213 |        |          | the rs#/rd field is zero-extended to get the actual      |
 214 |        |          | 7-bit register number                                    |
 215 +--------+----------+----------------------------------------------------------+
 216 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 217 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 218 |        |          | get the actual 7-bit register number                     |
 219 +--------+----------+----------------------------------------------------------+
 220
 221 If a vs#/vd field is not present, it is as if it was present with a value that
 222 is the bitwise-or of all present vs#/vd fields.
 223
 224 * scalar register numbers do NOT increment when allocated in the
 225   hardware for-loop.  the same scalar register number is handed
 226   to every ALU.
 227
 228 * vector register numbers *DO* increase when allocated in the
 229   hardware for-loop.  sequentially-increasing register data
 230   is handed to sequential ALUs.
 231
 232 Vector Register Number Encoding
 233 ===============================
 234
 235 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number is derived from the
 236 corresponding 6-bit rs#/rd field:
 237
 238 +---------------------------------+
 239 | Actual 7-bit register number    |
 240 +===========+=============+=======+
 241 | Bit 6     | Bits 5:1    | Bit 0 |
 242 +-----------+-------------+-------+
 243 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 244 +-----------+-------------+-------+
 245
 246 For the 64 bit format, the 7 bit register is constructed from the 7 bit fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format the full range of up to 128 registers is directly available. This for both when either scalar or vector mode is set.
 247
 248 Load/Store Kind (lsk) Field Encoding
 249 ====================================
 250
 251 +--------+-----+--------------------------------------------------------------------------------+
 252 | vd/vs2 | vs1 | Meaning                                                                        |
 253 +========+=====+================================================================================+
 254 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 255 +--------+-----+--------------------------------------------------------------------------------+
 256 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 257 +--------+-----+--------------------------------------------------------------------------------+
 258 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 259 +--------+-----+--------------------------------------------------------------------------------+
 260 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 261 +--------+-----+--------------------------------------------------------------------------------+
 262
 263 Notes:
 264
 265 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
 266 * Complex strides may all be done with a general purpose vector of srcbases.
 267 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
 268 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
 269
 270 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
 271
 272
 273 Sub-Vector Length (svlen) Field Encoding
 274 =======================================================
 275
 276 +----------------+-------+
 277 | svlen Encoding | Value |
 278 +================+=======+
 279 | 00             | 4     |
 280 +----------------+-------+
 281 | 01             | 1     |
 282 +----------------+-------+
 283 | 10             | 2     |
 284 +----------------+-------+
 285 | 11             | 3     |
 286 +----------------+-------+
 287
 288 Predication (pred) Field Encoding
 289 =================================
 290
 291 +------+------------+--------------------+----------------------------------------+
 292 | pred | Mnemonic   | Predicate Register | Meaning                                |
 293 +======+============+====================+========================================+
 294 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 295 +------+------------+--------------------+----------------------------------------+
 296 | 001  | *Reserved* | *Reserved*         |                                        |
 297 +------+------------+--------------------+----------------------------------------+
 298 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 299 +------+------------+                    +----------------------------------------+
 300 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 301 +------+------------+--------------------+----------------------------------------+
 302 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 303 +------+------------+                    +----------------------------------------+
 304 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 305 +------+------------+--------------------+----------------------------------------+
 306 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 307 +------+------------+                    +----------------------------------------+
 308 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 309 +------+------------+--------------------+----------------------------------------+
 310
 311 Twin-predication (tpred) Field Encoding
 312 =======================================
 313
 314 +-------+------------+--------------------+----------------------------------------------+
 315 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 316 +=======+============+====================+==============================================+
 317 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 318 +-------+------------+--------------------+----------------------------------------------+
 319 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 320 +-------+------------+                    +----------------------------------------------+
 321 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 322 +-------+------------+                    +----------------------------------------------+
 323 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 324 +-------+------------+--------------------+----------------------------------------------+
 325 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 326 +-------+------------+--------------------+----------------------------------------------+
 327 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 328 +-------+------------+                    +----------------------------------------------+
 329 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 330 +-------+------------+                    +----------------------------------------------+
 331 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 332 +-------+------------+--------------------+----------------------------------------------+
 333
 334 Integer Element Type (itype) Field Encoding
 335 ===========================================
 336
 337 +------------+-------+--------------+--------------+-----------------+-------------------+
 338 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 339 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 340 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 341 +============+=======+==============+==============+=================+===================+
 342 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 343 |            +-------+--------------+--------------+-----------------+-------------------+
 344 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 345 |            +-------+--------------+--------------+-----------------+-------------------+
 346 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 347 |            +-------+--------------+--------------+-----------------+-------------------+
 348 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 349 +------------+-------+--------------+--------------+-----------------+-------------------+
 350 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 351 |            +-------+--------------+--------------+-----------------+-------------------+
 352 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 353 |            +-------+--------------+--------------+-----------------+-------------------+
 354 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 355 |            +-------+--------------+--------------+-----------------+-------------------+
 356 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 357 +------------+-------+--------------+--------------+-----------------+-------------------+
 358
 359 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 360
 361 Note: vector mode is effectively a type-cast of the register file
 362 as if it was a sequential array being typecast to typedef itype[]
 363 (c syntax).  The starting point of the "typecast" is the vector
 364 register rs#/rd.
 365
 366 Example: if itype=0b10 (u16), and rd is set to "vector", and
 367 VL is set to 4, the 64-bit register at rd is subdivided into
 368 *FOUR* 16-bit destination elements.  It is *NOT* four
 369 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 370 that are sign-extended from the source width size out to 64-bit,
 371 because that is itype=0b00 (uXLEN).
 372
 373 Signedness Decision Procedure
 374 =============================
 375
 376 1. If the opcode field is either OP or OP-IMM, then
 377     1. Signedness is Unsigned.
 378 2. If the opcode field is either OP-32 or OP-IMM-32, then
 379     1. Signedness is Signed.
 380 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 381     1. Signedness uses the encoded value.
 382 4. Otherwise,
 383     1. Signedness is Unsigned.
 384
 385 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
 386                fmv.x.wu
 387
 388 Vector Type and Predication 5-bit (vtp5) Field Encoding
 389 =======================================================
 390
 391 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 392 different value for every occurrence.
 393
 394 +-------+-----------+-----------+
 395 | vtp5  | pred      | svlen     |
 396 +=======+===========+===========+
 397 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 398 +-------+           |           |
 399 | 01XXX |           |           |
 400 +-------+           |           |
 401 | 000XX |           |           |
 402 +-------+-----------+-----------+
 403 | 001XX | *Reserved*            |
 404 +-------+-----------------------+
 405
 406 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 407 ================================================================
 408
 409 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 410 different value for every occurrence.
 411
 412 +--------+------------+---------+------------+------------+
 413 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 414 +========+============+=========+============+============+
 415 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 416 +--------+            |         |            |            |
 417 | XX00XX |            |         |            |            |
 418 +--------+------------+---------+------------+------------+
 419 | XX01XX | *Reserved*                                     |
 420 +--------+------------------------------------------------+
 421
 422 vitp7 field: only tpred=
 423
 424 +---------+------------+----------+-------------+------------+
 425 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 426 +=========+============+==========+=============+============+
 427 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 428 +---------+------------+----------+-------------+------------+
 429
 430 48-bit Instruction Encoding Decision Procedure
 431 ==============================================
 432
 433 In the following decision procedure, *Reserved* means that there is not yet a
 434 defined 48-bit instruction encoding for the base instruction.
 435
 436 1. If the base instruction is a load instruction, then
 437     a. If the base instruction is an I-type instruction, then
 438         1. The encoding is P48-LD-type.
 439     b. Otherwise
 440         1. The encoding is *Reserved*.
 441 2. If the base instruction is a store instruction, then
 442     a. If the base instruction is an S-type instruction, then
 443         1. The encoding is P48-ST-type.
 444     b. Otherwise
 445         1. The encoding is *Reserved*.
 446 3. If the base instruction is a SYSTEM instruction, then
 447     a. The encoding is *Reserved*.
 448 4. If the base instruction is an integer instruction, then
 449     a. If the base instruction is an R-type instruction, then
 450         1. The encoding is P48-R-type.
 451     b. If the base instruction is an I-type instruction, then
 452         1. The encoding is P48-I-type.
 453     c. If the base instruction is an S-type instruction, then
 454         1. The encoding is *Reserved*.
 455     d. If the base instruction is an B-type instruction, then
 456         1. The encoding is *Reserved*.
 457     e. If the base instruction is an U-type instruction, then
 458         1. The encoding is P48-U-type.
 459     f. If the base instruction is an J-type instruction, then
 460         1. The encoding is *Reserved*.
 461     g. Otherwise
 462         1. The encoding is *Reserved*.
 463 5. If the base instruction is a floating-point instruction, then
 464     a. If the base instruction is an R-type instruction, then
 465         1. The encoding is P48-FR-type.
 466     b. If the base instruction is an I-type instruction, then
 467         1. The encoding is P48-FI-type.
 468     c. If the base instruction is an S-type instruction, then
 469         1. The encoding is *Reserved*.
 470     d. If the base instruction is an B-type instruction, then
 471         1. The encoding is *Reserved*.
 472     e. If the base instruction is an U-type instruction, then
 473         1. The encoding is *Reserved*.
 474     f. If the base instruction is an J-type instruction, then
 475         1. The encoding is *Reserved*.
 476     g. If the base instruction is an R4-type instruction, then
 477         1. The encoding is P48-FR4-type.
 478     h. Otherwise
 479         1. The encoding is *Reserved*.
 480 6. Otherwise
 481     a. The encoding is *Reserved*.
 482
 483 CSR Registers
 484 =============
 485
 486 +--------+-----------------+---------------------------------------------------+
 487 | Name   | Legal Values    | Meaning                                           |
 488 +========+=================+===================================================+
 489 | VL     | 0 <= VL <= XLEN | Vector Length. The number of sub-vectors operated |
 490 |        |                 | on by vector instructions.                        |
 491 +--------+-----------------+---------------------------------------------------+
 492 | Vstart | 0 <= VL < XLEN  | The sub-vector index to start execution at.       |
 493 |        |                 | Successful completion of all elements in a vector |
 494 |        |                 | instruction sets Vstart to 0. Set to the index of |
 495 |        |                 | the failing sub-vector when a vector instruction  |
 496 |        |                 | traps.  Used to resume execution of vector        |
 497 |        |                 | instructions after a trap. Is *NOT* "slow"        |
 498 +--------+-----------------+---------------------------------------------------+
 499
 500 SetVL
 501 =====
 502
 503 setvl rd, rs1, imm
 504
 505 imm is the amount of space allocated from the register file by the compiler.
 506
 507 Pseudocode:
 508
 509 1. Trap if imm > XLEN.
 510 2. If rs1 is x0, then
 511     1. Set VL to imm.
 512 3. Else If regs[rs1] > 2 * imm, then
 513     1. Set VL to XLEN.
 514 4. Else If regs[rs1] > imm, then
 515     1. Set VL to regs[rs1] / 2 rounded down.
 516 5. Otherwise,
 517     1. Set VL to regs[rs1].
 518 6. Set regs[rd] to VL.
 519
 520 Additional Instructions
 521 =======================
 522
 523 Add instructions to convert between integer types.
 524
 525 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
 526 lengths of the source and destination won't necessarily match.
 527
 528 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 529
 530 Add instructions to transpose (2-4)x(2-4) element matrices.
 531
 532 Add instructions to insert or extract a sub-vector from a vector, with the index
 533 allowed to be both immediate and from a register (*immediate can be covered partly
 534 by twin-predication, register cannot: requires MV.X aka VSELECT*)
 535
 536 Add a register gather instruction (aka MV.X)
 537
 538 # Open questions <a name="questions"></a>
 539
 540 What is SUBVL and how does it work
 541
 542 --
 543
 544 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64 where both CSRs may be stored internally in only 6 bits.
 545
 546 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
 547
 548 In addition, setting a hardware loop to zero turning instructions into NOPs, um, just branch over them, to start the first loop at the end, on the test for loop variable being zero, a la c "while do" instead of "do while".
 549
 550 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that it only goes to a max of 63 rather than 64?
 551
 552 --
 553
 554 Should these questions be moved to Discussion subpage
 555
 556 --
 557
 558 Is MV.X good enough a substitute for swizzle?
 559
 560 --
 561
 562 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary